whiterose

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Kconfig (67071B)


      1 # SPDX-License-Identifier: GPL-2.0
      2 config ARM
      3 	bool
      4 	default y
      5 	select ARCH_32BIT_OFF_T
      6 	select ARCH_CLOCKSOURCE_DATA
      7 	select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
      8 	select ARCH_HAS_DEBUG_VIRTUAL if MMU
      9 	select ARCH_HAS_DEVMEM_IS_ALLOWED
     10 	select ARCH_HAS_ELF_RANDOMIZE
     11 	select ARCH_HAS_FORTIFY_SOURCE
     12 	select ARCH_HAS_KCOV
     13 	select ARCH_HAS_MEMBARRIER_SYNC_CORE
     14 	select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
     15 	select ARCH_HAS_PHYS_TO_DMA
     16 	select ARCH_HAS_SETUP_DMA_OPS
     17 	select ARCH_HAS_SET_MEMORY
     18 	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
     19 	select ARCH_HAS_STRICT_MODULE_RWX if MMU
     20 	select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
     21 	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
     22 	select ARCH_HAVE_CUSTOM_GPIO_H
     23 	select ARCH_HAS_GCOV_PROFILE_ALL
     24 	select ARCH_MIGHT_HAVE_PC_PARPORT
     25 	select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
     26 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
     27 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
     28 	select ARCH_SUPPORTS_ATOMIC_RMW
     29 	select ARCH_USE_BUILTIN_BSWAP
     30 	select ARCH_USE_CMPXCHG_LOCKREF
     31 	select ARCH_WANT_IPC_PARSE_VERSION
     32 	select BUILDTIME_EXTABLE_SORT if MMU
     33 	select CLONE_BACKWARDS
     34 	select CPU_PM if SUSPEND || CPU_IDLE
     35 	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
     36 	select DMA_DECLARE_COHERENT
     37 	select DMA_REMAP if MMU
     38 	select EDAC_SUPPORT
     39 	select EDAC_ATOMIC_SCRUB
     40 	select GENERIC_ALLOCATOR
     41 	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
     42 	select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
     43 	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
     44 	select GENERIC_CPU_AUTOPROBE
     45 	select GENERIC_EARLY_IOREMAP
     46 	select GENERIC_IDLE_POLL_SETUP
     47 	select GENERIC_IRQ_PROBE
     48 	select GENERIC_IRQ_SHOW
     49 	select GENERIC_IRQ_SHOW_LEVEL
     50 	select GENERIC_PCI_IOMAP
     51 	select GENERIC_SCHED_CLOCK
     52 	select GENERIC_SMP_IDLE_THREAD
     53 	select GENERIC_STRNCPY_FROM_USER
     54 	select GENERIC_STRNLEN_USER
     55 	select HANDLE_DOMAIN_IRQ
     56 	select HARDIRQS_SW_RESEND
     57 	select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
     58 	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
     59 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
     60 	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
     61 	select HAVE_ARCH_MMAP_RND_BITS if MMU
     62 	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
     63 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
     64 	select HAVE_ARCH_TRACEHOOK
     65 	select HAVE_ARM_SMCCC if CPU_V7
     66 	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
     67 	select HAVE_CONTEXT_TRACKING
     68 	select HAVE_C_RECORDMCOUNT
     69 	select HAVE_DEBUG_KMEMLEAK
     70 	select HAVE_DMA_CONTIGUOUS if MMU
     71 	select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
     72 	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
     73 	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
     74 	select HAVE_EXIT_THREAD
     75 	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
     76 	select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL
     77 	select HAVE_FUNCTION_TRACER if !XIP_KERNEL
     78 	select HAVE_GCC_PLUGINS
     79 	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
     80 	select HAVE_IDE if PCI || ISA || PCMCIA
     81 	select HAVE_IRQ_TIME_ACCOUNTING
     82 	select HAVE_KERNEL_GZIP
     83 	select HAVE_KERNEL_LZ4
     84 	select HAVE_KERNEL_LZMA
     85 	select HAVE_KERNEL_LZO
     86 	select HAVE_KERNEL_XZ
     87 	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
     88 	select HAVE_KRETPROBES if HAVE_KPROBES
     89 	select HAVE_MOD_ARCH_SPECIFIC
     90 	select HAVE_NMI
     91 	select HAVE_OPROFILE if HAVE_PERF_EVENTS
     92 	select HAVE_OPTPROBES if !THUMB2_KERNEL
     93 	select HAVE_PERF_EVENTS
     94 	select HAVE_PERF_REGS
     95 	select HAVE_PERF_USER_STACK_DUMP
     96 	select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
     97 	select HAVE_REGS_AND_STACK_ACCESS_API
     98 	select HAVE_RSEQ
     99 	select HAVE_STACKPROTECTOR
    100 	select HAVE_SYSCALL_TRACEPOINTS
    101 	select HAVE_UID16
    102 	select HAVE_VIRT_CPU_ACCOUNTING_GEN
    103 	select IRQ_FORCED_THREADING
    104 	select MODULES_USE_ELF_REL
    105 	select NEED_DMA_MAP_STATE
    106 	select OF_EARLY_FLATTREE if OF
    107 	select OLD_SIGACTION
    108 	select OLD_SIGSUSPEND3
    109 	select PCI_SYSCALL if PCI
    110 	select PERF_USE_VMALLOC
    111 	select REFCOUNT_FULL
    112 	select RTC_LIB
    113 	select SYS_SUPPORTS_APM_EMULATION
    114 	# Above selects are sorted alphabetically; please add new ones
    115 	# according to that.  Thanks.
    116 	help
    117 	  The ARM series is a line of low-power-consumption RISC chip designs
    118 	  licensed by ARM Ltd and targeted at embedded applications and
    119 	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
    120 	  manufactured, but legacy ARM-based PC hardware remains popular in
    121 	  Europe.  There is an ARM Linux project with a web page at
    122 	  <http://www.arm.linux.org.uk/>.
    123 
    124 config ARM_HAS_SG_CHAIN
    125 	bool
    126 
    127 config ARM_DMA_USE_IOMMU
    128 	bool
    129 	select ARM_HAS_SG_CHAIN
    130 	select NEED_SG_DMA_LENGTH
    131 
    132 if ARM_DMA_USE_IOMMU
    133 
    134 config ARM_DMA_IOMMU_ALIGNMENT
    135 	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
    136 	range 4 9
    137 	default 8
    138 	help
    139 	  DMA mapping framework by default aligns all buffers to the smallest
    140 	  PAGE_SIZE order which is greater than or equal to the requested buffer
    141 	  size. This works well for buffers up to a few hundreds kilobytes, but
    142 	  for larger buffers it just a waste of address space. Drivers which has
    143 	  relatively small addressing window (like 64Mib) might run out of
    144 	  virtual space with just a few allocations.
    145 
    146 	  With this parameter you can specify the maximum PAGE_SIZE order for
    147 	  DMA IOMMU buffers. Larger buffers will be aligned only to this
    148 	  specified order. The order is expressed as a power of two multiplied
    149 	  by the PAGE_SIZE.
    150 
    151 endif
    152 
    153 config SYS_SUPPORTS_APM_EMULATION
    154 	bool
    155 
    156 config HAVE_TCM
    157 	bool
    158 	select GENERIC_ALLOCATOR
    159 
    160 config HAVE_PROC_CPU
    161 	bool
    162 
    163 config NO_IOPORT_MAP
    164 	bool
    165 
    166 config SBUS
    167 	bool
    168 
    169 config STACKTRACE_SUPPORT
    170 	bool
    171 	default y
    172 
    173 config LOCKDEP_SUPPORT
    174 	bool
    175 	default y
    176 
    177 config TRACE_IRQFLAGS_SUPPORT
    178 	bool
    179 	default !CPU_V7M
    180 
    181 config RWSEM_XCHGADD_ALGORITHM
    182 	bool
    183 	default y
    184 
    185 config ARCH_HAS_ILOG2_U32
    186 	bool
    187 
    188 config ARCH_HAS_ILOG2_U64
    189 	bool
    190 
    191 config ARCH_HAS_BANDGAP
    192 	bool
    193 
    194 config FIX_EARLYCON_MEM
    195 	def_bool y if MMU
    196 
    197 config GENERIC_HWEIGHT
    198 	bool
    199 	default y
    200 
    201 config GENERIC_CALIBRATE_DELAY
    202 	bool
    203 	default y
    204 
    205 config ARCH_MAY_HAVE_PC_FDC
    206 	bool
    207 
    208 config ZONE_DMA
    209 	bool
    210 
    211 config ARCH_SUPPORTS_UPROBES
    212 	def_bool y
    213 
    214 config ARCH_HAS_DMA_SET_COHERENT_MASK
    215 	bool
    216 
    217 config GENERIC_ISA_DMA
    218 	bool
    219 
    220 config FIQ
    221 	bool
    222 
    223 config NEED_RET_TO_USER
    224 	bool
    225 
    226 config ARCH_MTD_XIP
    227 	bool
    228 
    229 config ARM_PATCH_PHYS_VIRT
    230 	bool "Patch physical to virtual translations at runtime" if EMBEDDED
    231 	default y
    232 	depends on !XIP_KERNEL && MMU
    233 	help
    234 	  Patch phys-to-virt and virt-to-phys translation functions at
    235 	  boot and module load time according to the position of the
    236 	  kernel in system memory.
    237 
    238 	  This can only be used with non-XIP MMU kernels where the base
    239 	  of physical memory is at a 16MB boundary.
    240 
    241 	  Only disable this option if you know that you do not require
    242 	  this feature (eg, building a kernel for a single machine) and
    243 	  you need to shrink the kernel to the minimal size.
    244 
    245 config NEED_MACH_IO_H
    246 	bool
    247 	help
    248 	  Select this when mach/io.h is required to provide special
    249 	  definitions for this platform.  The need for mach/io.h should
    250 	  be avoided when possible.
    251 
    252 config NEED_MACH_MEMORY_H
    253 	bool
    254 	help
    255 	  Select this when mach/memory.h is required to provide special
    256 	  definitions for this platform.  The need for mach/memory.h should
    257 	  be avoided when possible.
    258 
    259 config PHYS_OFFSET
    260 	hex "Physical address of main memory" if MMU
    261 	depends on !ARM_PATCH_PHYS_VIRT
    262 	default DRAM_BASE if !MMU
    263 	default 0x00000000 if ARCH_EBSA110 || \
    264 			ARCH_FOOTBRIDGE || \
    265 			ARCH_INTEGRATOR || \
    266 			ARCH_IOP13XX || \
    267 			ARCH_KS8695 || \
    268 			ARCH_REALVIEW
    269 	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
    270 	default 0x20000000 if ARCH_S5PV210
    271 	default 0xc0000000 if ARCH_SA1100
    272 	help
    273 	  Please provide the physical address corresponding to the
    274 	  location of main memory in your system.
    275 
    276 config GENERIC_BUG
    277 	def_bool y
    278 	depends on BUG
    279 
    280 config PGTABLE_LEVELS
    281 	int
    282 	default 3 if ARM_LPAE
    283 	default 2
    284 
    285 menu "System Type"
    286 
    287 config MMU
    288 	bool "MMU-based Paged Memory Management Support"
    289 	default y
    290 	help
    291 	  Select if you want MMU-based virtualised addressing space
    292 	  support by paged memory management. If unsure, say 'Y'.
    293 
    294 config ARCH_MMAP_RND_BITS_MIN
    295 	default 8
    296 
    297 config ARCH_MMAP_RND_BITS_MAX
    298 	default 14 if PAGE_OFFSET=0x40000000
    299 	default 15 if PAGE_OFFSET=0x80000000
    300 	default 16
    301 
    302 #
    303 # The "ARM system type" choice list is ordered alphabetically by option
    304 # text.  Please add new entries in the option alphabetic order.
    305 #
    306 choice
    307 	prompt "ARM system type"
    308 	default ARM_SINGLE_ARMV7M if !MMU
    309 	default ARCH_MULTIPLATFORM if MMU
    310 
    311 config ARCH_MULTIPLATFORM
    312 	bool "Allow multiple platforms to be selected"
    313 	depends on MMU
    314 	select ARM_HAS_SG_CHAIN
    315 	select ARM_PATCH_PHYS_VIRT
    316 	select AUTO_ZRELADDR
    317 	select TIMER_OF
    318 	select COMMON_CLK
    319 	select GENERIC_CLOCKEVENTS
    320 	select GENERIC_IRQ_MULTI_HANDLER
    321 	select HAVE_PCI
    322 	select PCI_DOMAINS_GENERIC if PCI
    323 	select SPARSE_IRQ
    324 	select USE_OF
    325 
    326 config ARM_SINGLE_ARMV7M
    327 	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
    328 	depends on !MMU
    329 	select ARM_NVIC
    330 	select AUTO_ZRELADDR
    331 	select TIMER_OF
    332 	select COMMON_CLK
    333 	select CPU_V7M
    334 	select GENERIC_CLOCKEVENTS
    335 	select NO_IOPORT_MAP
    336 	select SPARSE_IRQ
    337 	select USE_OF
    338 
    339 config ARCH_EBSA110
    340 	bool "EBSA-110"
    341 	select ARCH_USES_GETTIMEOFFSET
    342 	select CPU_SA110
    343 	select ISA
    344 	select NEED_MACH_IO_H
    345 	select NEED_MACH_MEMORY_H
    346 	select NO_IOPORT_MAP
    347 	help
    348 	  This is an evaluation board for the StrongARM processor available
    349 	  from Digital. It has limited hardware on-board, including an
    350 	  Ethernet interface, two PCMCIA sockets, two serial ports and a
    351 	  parallel port.
    352 
    353 config ARCH_EP93XX
    354 	bool "EP93xx-based"
    355 	select ARCH_SPARSEMEM_ENABLE
    356 	select ARM_AMBA
    357 	imply ARM_PATCH_PHYS_VIRT
    358 	select ARM_VIC
    359 	select AUTO_ZRELADDR
    360 	select CLKDEV_LOOKUP
    361 	select CLKSRC_MMIO
    362 	select CPU_ARM920T
    363 	select GENERIC_CLOCKEVENTS
    364 	select GPIOLIB
    365 	help
    366 	  This enables support for the Cirrus EP93xx series of CPUs.
    367 
    368 config ARCH_FOOTBRIDGE
    369 	bool "FootBridge"
    370 	select CPU_SA110
    371 	select FOOTBRIDGE
    372 	select GENERIC_CLOCKEVENTS
    373 	select HAVE_IDE
    374 	select NEED_MACH_IO_H if !MMU
    375 	select NEED_MACH_MEMORY_H
    376 	help
    377 	  Support for systems based on the DC21285 companion chip
    378 	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
    379 
    380 config ARCH_NETX
    381 	bool "Hilscher NetX based"
    382 	select ARM_VIC
    383 	select CLKSRC_MMIO
    384 	select CPU_ARM926T
    385 	select GENERIC_CLOCKEVENTS
    386 	help
    387 	  This enables support for systems based on the Hilscher NetX Soc
    388 
    389 config ARCH_IOP13XX
    390 	bool "IOP13xx-based"
    391 	depends on MMU
    392 	select CPU_XSC3
    393 	select NEED_MACH_MEMORY_H
    394 	select NEED_RET_TO_USER
    395 	select FORCE_PCI
    396 	select PLAT_IOP
    397 	select VMSPLIT_1G
    398 	select SPARSE_IRQ
    399 	help
    400 	  Support for Intel's IOP13XX (XScale) family of processors.
    401 
    402 config ARCH_IOP32X
    403 	bool "IOP32x-based"
    404 	depends on MMU
    405 	select CPU_XSCALE
    406 	select GPIO_IOP
    407 	select GPIOLIB
    408 	select NEED_RET_TO_USER
    409 	select FORCE_PCI
    410 	select PLAT_IOP
    411 	help
    412 	  Support for Intel's 80219 and IOP32X (XScale) family of
    413 	  processors.
    414 
    415 config ARCH_IOP33X
    416 	bool "IOP33x-based"
    417 	depends on MMU
    418 	select CPU_XSCALE
    419 	select GPIO_IOP
    420 	select GPIOLIB
    421 	select NEED_RET_TO_USER
    422 	select FORCE_PCI
    423 	select PLAT_IOP
    424 	help
    425 	  Support for Intel's IOP33X (XScale) family of processors.
    426 
    427 config ARCH_IXP4XX
    428 	bool "IXP4xx-based"
    429 	depends on MMU
    430 	select ARCH_HAS_DMA_SET_COHERENT_MASK
    431 	select ARCH_SUPPORTS_BIG_ENDIAN
    432 	select CLKSRC_MMIO
    433 	select CPU_XSCALE
    434 	select DMABOUNCE if PCI
    435 	select GENERIC_CLOCKEVENTS
    436 	select GPIOLIB
    437 	select HAVE_PCI
    438 	select NEED_MACH_IO_H
    439 	select USB_EHCI_BIG_ENDIAN_DESC
    440 	select USB_EHCI_BIG_ENDIAN_MMIO
    441 	help
    442 	  Support for Intel's IXP4XX (XScale) family of processors.
    443 
    444 config ARCH_DOVE
    445 	bool "Marvell Dove"
    446 	select CPU_PJ4
    447 	select GENERIC_CLOCKEVENTS
    448 	select GENERIC_IRQ_MULTI_HANDLER
    449 	select GPIOLIB
    450 	select HAVE_PCI
    451 	select MVEBU_MBUS
    452 	select PINCTRL
    453 	select PINCTRL_DOVE
    454 	select PLAT_ORION_LEGACY
    455 	select SPARSE_IRQ
    456 	select PM_GENERIC_DOMAINS if PM
    457 	help
    458 	  Support for the Marvell Dove SoC 88AP510
    459 
    460 config ARCH_KS8695
    461 	bool "Micrel/Kendin KS8695"
    462 	select CLKSRC_MMIO
    463 	select CPU_ARM922T
    464 	select GENERIC_CLOCKEVENTS
    465 	select GPIOLIB
    466 	select NEED_MACH_MEMORY_H
    467 	help
    468 	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
    469 	  System-on-Chip devices.
    470 
    471 config ARCH_W90X900
    472 	bool "Nuvoton W90X900 CPU"
    473 	select CLKDEV_LOOKUP
    474 	select CLKSRC_MMIO
    475 	select CPU_ARM926T
    476 	select GENERIC_CLOCKEVENTS
    477 	select GPIOLIB
    478 	help
    479 	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
    480 	  At present, the w90x900 has been renamed nuc900, regarding
    481 	  the ARM series product line, you can login the following
    482 	  link address to know more.
    483 
    484 	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
    485 		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
    486 
    487 config ARCH_LPC32XX
    488 	bool "NXP LPC32XX"
    489 	select ARM_AMBA
    490 	select CLKDEV_LOOKUP
    491 	select CLKSRC_LPC32XX
    492 	select COMMON_CLK
    493 	select CPU_ARM926T
    494 	select GENERIC_CLOCKEVENTS
    495 	select GENERIC_IRQ_MULTI_HANDLER
    496 	select GPIOLIB
    497 	select SPARSE_IRQ
    498 	select USE_OF
    499 	help
    500 	  Support for the NXP LPC32XX family of processors
    501 
    502 config ARCH_PXA
    503 	bool "PXA2xx/PXA3xx-based"
    504 	depends on MMU
    505 	select ARCH_MTD_XIP
    506 	select ARM_CPU_SUSPEND if PM
    507 	select AUTO_ZRELADDR
    508 	select COMMON_CLK
    509 	select CLKDEV_LOOKUP
    510 	select CLKSRC_PXA
    511 	select CLKSRC_MMIO
    512 	select TIMER_OF
    513 	select CPU_XSCALE if !CPU_XSC3
    514 	select GENERIC_CLOCKEVENTS
    515 	select GENERIC_IRQ_MULTI_HANDLER
    516 	select GPIO_PXA
    517 	select GPIOLIB
    518 	select HAVE_IDE
    519 	select IRQ_DOMAIN
    520 	select PLAT_PXA
    521 	select SPARSE_IRQ
    522 	help
    523 	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
    524 
    525 config ARCH_RPC
    526 	bool "RiscPC"
    527 	depends on MMU
    528 	select ARCH_ACORN
    529 	select ARCH_MAY_HAVE_PC_FDC
    530 	select ARCH_SPARSEMEM_ENABLE
    531 	select ARCH_USES_GETTIMEOFFSET
    532 	select CPU_SA110
    533 	select FIQ
    534 	select HAVE_IDE
    535 	select HAVE_PATA_PLATFORM
    536 	select ISA_DMA_API
    537 	select NEED_MACH_IO_H
    538 	select NEED_MACH_MEMORY_H
    539 	select NO_IOPORT_MAP
    540 	help
    541 	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
    542 	  CD-ROM interface, serial and parallel port, and the floppy drive.
    543 
    544 config ARCH_SA1100
    545 	bool "SA1100-based"
    546 	select ARCH_MTD_XIP
    547 	select ARCH_SPARSEMEM_ENABLE
    548 	select CLKDEV_LOOKUP
    549 	select CLKSRC_MMIO
    550 	select CLKSRC_PXA
    551 	select TIMER_OF if OF
    552 	select CPU_FREQ
    553 	select CPU_SA1100
    554 	select GENERIC_CLOCKEVENTS
    555 	select GENERIC_IRQ_MULTI_HANDLER
    556 	select GPIOLIB
    557 	select HAVE_IDE
    558 	select IRQ_DOMAIN
    559 	select ISA
    560 	select NEED_MACH_MEMORY_H
    561 	select SPARSE_IRQ
    562 	help
    563 	  Support for StrongARM 11x0 based boards.
    564 
    565 config ARCH_S3C24XX
    566 	bool "Samsung S3C24XX SoCs"
    567 	select ATAGS
    568 	select CLKDEV_LOOKUP
    569 	select CLKSRC_SAMSUNG_PWM
    570 	select GENERIC_CLOCKEVENTS
    571 	select GPIO_SAMSUNG
    572 	select GPIOLIB
    573 	select GENERIC_IRQ_MULTI_HANDLER
    574 	select HAVE_S3C2410_I2C if I2C
    575 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
    576 	select HAVE_S3C_RTC if RTC_CLASS
    577 	select NEED_MACH_IO_H
    578 	select SAMSUNG_ATAGS
    579 	select USE_OF
    580 	help
    581 	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
    582 	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
    583 	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
    584 	  Samsung SMDK2410 development board (and derivatives).
    585 
    586 config ARCH_DAVINCI
    587 	bool "TI DaVinci"
    588 	select ARCH_HAS_HOLES_MEMORYMODEL
    589 	select COMMON_CLK
    590 	select CPU_ARM926T
    591 	select GENERIC_ALLOCATOR
    592 	select GENERIC_CLOCKEVENTS
    593 	select GENERIC_IRQ_CHIP
    594 	select GENERIC_IRQ_MULTI_HANDLER
    595 	select GPIOLIB
    596 	select HAVE_IDE
    597 	select PM_GENERIC_DOMAINS if PM
    598 	select PM_GENERIC_DOMAINS_OF if PM && OF
    599 	select REGMAP_MMIO
    600 	select RESET_CONTROLLER
    601 	select SPARSE_IRQ
    602 	select USE_OF
    603 	select ZONE_DMA
    604 	help
    605 	  Support for TI's DaVinci platform.
    606 
    607 config ARCH_OMAP1
    608 	bool "TI OMAP1"
    609 	depends on MMU
    610 	select ARCH_HAS_HOLES_MEMORYMODEL
    611 	select ARCH_OMAP
    612 	select CLKDEV_LOOKUP
    613 	select CLKSRC_MMIO
    614 	select GENERIC_CLOCKEVENTS
    615 	select GENERIC_IRQ_CHIP
    616 	select GENERIC_IRQ_MULTI_HANDLER
    617 	select GPIOLIB
    618 	select HAVE_IDE
    619 	select IRQ_DOMAIN
    620 	select NEED_MACH_IO_H if PCCARD
    621 	select NEED_MACH_MEMORY_H
    622 	select SPARSE_IRQ
    623 	help
    624 	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
    625 
    626 endchoice
    627 
    628 menu "Multiple platform selection"
    629 	depends on ARCH_MULTIPLATFORM
    630 
    631 comment "CPU Core family selection"
    632 
    633 config ARCH_MULTI_V4
    634 	bool "ARMv4 based platforms (FA526)"
    635 	depends on !ARCH_MULTI_V6_V7
    636 	select ARCH_MULTI_V4_V5
    637 	select CPU_FA526
    638 
    639 config ARCH_MULTI_V4T
    640 	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
    641 	depends on !ARCH_MULTI_V6_V7
    642 	select ARCH_MULTI_V4_V5
    643 	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
    644 		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
    645 		CPU_ARM925T || CPU_ARM940T)
    646 
    647 config ARCH_MULTI_V5
    648 	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
    649 	depends on !ARCH_MULTI_V6_V7
    650 	select ARCH_MULTI_V4_V5
    651 	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
    652 		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
    653 		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
    654 
    655 config ARCH_MULTI_V4_V5
    656 	bool
    657 
    658 config ARCH_MULTI_V6
    659 	bool "ARMv6 based platforms (ARM11)"
    660 	select ARCH_MULTI_V6_V7
    661 	select CPU_V6K
    662 
    663 config ARCH_MULTI_V7
    664 	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
    665 	default y
    666 	select ARCH_MULTI_V6_V7
    667 	select CPU_V7
    668 	select HAVE_SMP
    669 
    670 config ARCH_MULTI_V6_V7
    671 	bool
    672 	select MIGHT_HAVE_CACHE_L2X0
    673 
    674 config ARCH_MULTI_CPU_AUTO
    675 	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
    676 	select ARCH_MULTI_V5
    677 
    678 endmenu
    679 
    680 config ARCH_VIRT
    681 	bool "Dummy Virtual Machine"
    682 	depends on ARCH_MULTI_V7
    683 	select ARM_AMBA
    684 	select ARM_GIC
    685 	select ARM_GIC_V2M if PCI
    686 	select ARM_GIC_V3
    687 	select ARM_GIC_V3_ITS if PCI
    688 	select ARM_PSCI
    689 	select HAVE_ARM_ARCH_TIMER
    690 	select ARCH_SUPPORTS_BIG_ENDIAN
    691 
    692 #
    693 # This is sorted alphabetically by mach-* pathname.  However, plat-*
    694 # Kconfigs may be included either alphabetically (according to the
    695 # plat- suffix) or along side the corresponding mach-* source.
    696 #
    697 source "arch/arm/mach-actions/Kconfig"
    698 
    699 source "arch/arm/mach-alpine/Kconfig"
    700 
    701 source "arch/arm/mach-artpec/Kconfig"
    702 
    703 source "arch/arm/mach-asm9260/Kconfig"
    704 
    705 source "arch/arm/mach-aspeed/Kconfig"
    706 
    707 source "arch/arm/mach-at91/Kconfig"
    708 
    709 source "arch/arm/mach-axxia/Kconfig"
    710 
    711 source "arch/arm/mach-bcm/Kconfig"
    712 
    713 source "arch/arm/mach-berlin/Kconfig"
    714 
    715 source "arch/arm/mach-clps711x/Kconfig"
    716 
    717 source "arch/arm/mach-cns3xxx/Kconfig"
    718 
    719 source "arch/arm/mach-davinci/Kconfig"
    720 
    721 source "arch/arm/mach-digicolor/Kconfig"
    722 
    723 source "arch/arm/mach-dove/Kconfig"
    724 
    725 source "arch/arm/mach-ep93xx/Kconfig"
    726 
    727 source "arch/arm/mach-exynos/Kconfig"
    728 source "arch/arm/plat-samsung/Kconfig"
    729 
    730 source "arch/arm/mach-footbridge/Kconfig"
    731 
    732 source "arch/arm/mach-gemini/Kconfig"
    733 
    734 source "arch/arm/mach-highbank/Kconfig"
    735 
    736 source "arch/arm/mach-hisi/Kconfig"
    737 
    738 source "arch/arm/mach-imx/Kconfig"
    739 
    740 source "arch/arm/mach-integrator/Kconfig"
    741 
    742 source "arch/arm/mach-iop13xx/Kconfig"
    743 
    744 source "arch/arm/mach-iop32x/Kconfig"
    745 
    746 source "arch/arm/mach-iop33x/Kconfig"
    747 
    748 source "arch/arm/mach-ixp4xx/Kconfig"
    749 
    750 source "arch/arm/mach-keystone/Kconfig"
    751 
    752 source "arch/arm/mach-ks8695/Kconfig"
    753 
    754 source "arch/arm/mach-mediatek/Kconfig"
    755 
    756 source "arch/arm/mach-meson/Kconfig"
    757 
    758 source "arch/arm/mach-milbeaut/Kconfig"
    759 
    760 source "arch/arm/mach-mmp/Kconfig"
    761 
    762 source "arch/arm/mach-moxart/Kconfig"
    763 
    764 source "arch/arm/mach-mv78xx0/Kconfig"
    765 
    766 source "arch/arm/mach-mvebu/Kconfig"
    767 
    768 source "arch/arm/mach-mxs/Kconfig"
    769 
    770 source "arch/arm/mach-netx/Kconfig"
    771 
    772 source "arch/arm/mach-nomadik/Kconfig"
    773 
    774 source "arch/arm/mach-npcm/Kconfig"
    775 
    776 source "arch/arm/mach-nspire/Kconfig"
    777 
    778 source "arch/arm/plat-omap/Kconfig"
    779 
    780 source "arch/arm/mach-omap1/Kconfig"
    781 
    782 source "arch/arm/mach-omap2/Kconfig"
    783 
    784 source "arch/arm/mach-orion5x/Kconfig"
    785 
    786 source "arch/arm/mach-oxnas/Kconfig"
    787 
    788 source "arch/arm/mach-picoxcell/Kconfig"
    789 
    790 source "arch/arm/mach-prima2/Kconfig"
    791 
    792 source "arch/arm/mach-pxa/Kconfig"
    793 source "arch/arm/plat-pxa/Kconfig"
    794 
    795 source "arch/arm/mach-qcom/Kconfig"
    796 
    797 source "arch/arm/mach-rda/Kconfig"
    798 
    799 source "arch/arm/mach-realview/Kconfig"
    800 
    801 source "arch/arm/mach-rockchip/Kconfig"
    802 
    803 source "arch/arm/mach-s3c24xx/Kconfig"
    804 
    805 source "arch/arm/mach-s3c64xx/Kconfig"
    806 
    807 source "arch/arm/mach-s5pv210/Kconfig"
    808 
    809 source "arch/arm/mach-sa1100/Kconfig"
    810 
    811 source "arch/arm/mach-shmobile/Kconfig"
    812 
    813 source "arch/arm/mach-socfpga/Kconfig"
    814 
    815 source "arch/arm/mach-spear/Kconfig"
    816 
    817 source "arch/arm/mach-sti/Kconfig"
    818 
    819 source "arch/arm/mach-stm32/Kconfig"
    820 
    821 source "arch/arm/mach-sunxi/Kconfig"
    822 
    823 source "arch/arm/mach-tango/Kconfig"
    824 
    825 source "arch/arm/mach-tegra/Kconfig"
    826 
    827 source "arch/arm/mach-u300/Kconfig"
    828 
    829 source "arch/arm/mach-uniphier/Kconfig"
    830 
    831 source "arch/arm/mach-ux500/Kconfig"
    832 
    833 source "arch/arm/mach-versatile/Kconfig"
    834 
    835 source "arch/arm/mach-vexpress/Kconfig"
    836 source "arch/arm/plat-versatile/Kconfig"
    837 
    838 source "arch/arm/mach-vt8500/Kconfig"
    839 
    840 source "arch/arm/mach-w90x900/Kconfig"
    841 
    842 source "arch/arm/mach-zx/Kconfig"
    843 
    844 source "arch/arm/mach-zynq/Kconfig"
    845 
    846 # ARMv7-M architecture
    847 config ARCH_EFM32
    848 	bool "Energy Micro efm32"
    849 	depends on ARM_SINGLE_ARMV7M
    850 	select GPIOLIB
    851 	help
    852 	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
    853 	  processors.
    854 
    855 config ARCH_LPC18XX
    856 	bool "NXP LPC18xx/LPC43xx"
    857 	depends on ARM_SINGLE_ARMV7M
    858 	select ARCH_HAS_RESET_CONTROLLER
    859 	select ARM_AMBA
    860 	select CLKSRC_LPC32XX
    861 	select PINCTRL
    862 	help
    863 	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
    864 	  high performance microcontrollers.
    865 
    866 config ARCH_MPS2
    867 	bool "ARM MPS2 platform"
    868 	depends on ARM_SINGLE_ARMV7M
    869 	select ARM_AMBA
    870 	select CLKSRC_MPS2
    871 	help
    872 	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
    873 	  with a range of available cores like Cortex-M3/M4/M7.
    874 
    875 	  Please, note that depends which Application Note is used memory map
    876 	  for the platform may vary, so adjustment of RAM base might be needed.
    877 
    878 # Definitions to make life easier
    879 config ARCH_ACORN
    880 	bool
    881 
    882 config PLAT_IOP
    883 	bool
    884 	select GENERIC_CLOCKEVENTS
    885 
    886 config PLAT_ORION
    887 	bool
    888 	select CLKSRC_MMIO
    889 	select COMMON_CLK
    890 	select GENERIC_IRQ_CHIP
    891 	select IRQ_DOMAIN
    892 
    893 config PLAT_ORION_LEGACY
    894 	bool
    895 	select PLAT_ORION
    896 
    897 config PLAT_PXA
    898 	bool
    899 
    900 config PLAT_VERSATILE
    901 	bool
    902 
    903 source "arch/arm/firmware/Kconfig"
    904 
    905 source "arch/arm/mm/Kconfig"
    906 
    907 config IWMMXT
    908 	bool "Enable iWMMXt support"
    909 	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
    910 	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
    911 	help
    912 	  Enable support for iWMMXt context switching at run time if
    913 	  running on a CPU that supports it.
    914 
    915 if !MMU
    916 source "arch/arm/Kconfig-nommu"
    917 endif
    918 
    919 config PJ4B_ERRATA_4742
    920 	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
    921 	depends on CPU_PJ4B && MACH_ARMADA_370
    922 	default y
    923 	help
    924 	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
    925 	  Event (WFE) IDLE states, a specific timing sensitivity exists between
    926 	  the retiring WFI/WFE instructions and the newly issued subsequent
    927 	  instructions.  This sensitivity can result in a CPU hang scenario.
    928 	  Workaround:
    929 	  The software must insert either a Data Synchronization Barrier (DSB)
    930 	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
    931 	  instruction
    932 
    933 config ARM_ERRATA_326103
    934 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
    935 	depends on CPU_V6
    936 	help
    937 	  Executing a SWP instruction to read-only memory does not set bit 11
    938 	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
    939 	  treat the access as a read, preventing a COW from occurring and
    940 	  causing the faulting task to livelock.
    941 
    942 config ARM_ERRATA_411920
    943 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
    944 	depends on CPU_V6 || CPU_V6K
    945 	help
    946 	  Invalidation of the Instruction Cache operation can
    947 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
    948 	  It does not affect the MPCore. This option enables the ARM Ltd.
    949 	  recommended workaround.
    950 
    951 config ARM_ERRATA_430973
    952 	bool "ARM errata: Stale prediction on replaced interworking branch"
    953 	depends on CPU_V7
    954 	help
    955 	  This option enables the workaround for the 430973 Cortex-A8
    956 	  r1p* erratum. If a code sequence containing an ARM/Thumb
    957 	  interworking branch is replaced with another code sequence at the
    958 	  same virtual address, whether due to self-modifying code or virtual
    959 	  to physical address re-mapping, Cortex-A8 does not recover from the
    960 	  stale interworking branch prediction. This results in Cortex-A8
    961 	  executing the new code sequence in the incorrect ARM or Thumb state.
    962 	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
    963 	  and also flushes the branch target cache at every context switch.
    964 	  Note that setting specific bits in the ACTLR register may not be
    965 	  available in non-secure mode.
    966 
    967 config ARM_ERRATA_458693
    968 	bool "ARM errata: Processor deadlock when a false hazard is created"
    969 	depends on CPU_V7
    970 	depends on !ARCH_MULTIPLATFORM
    971 	help
    972 	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
    973 	  erratum. For very specific sequences of memory operations, it is
    974 	  possible for a hazard condition intended for a cache line to instead
    975 	  be incorrectly associated with a different cache line. This false
    976 	  hazard might then cause a processor deadlock. The workaround enables
    977 	  the L1 caching of the NEON accesses and disables the PLD instruction
    978 	  in the ACTLR register. Note that setting specific bits in the ACTLR
    979 	  register may not be available in non-secure mode.
    980 
    981 config ARM_ERRATA_460075
    982 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
    983 	depends on CPU_V7
    984 	depends on !ARCH_MULTIPLATFORM
    985 	help
    986 	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
    987 	  erratum. Any asynchronous access to the L2 cache may encounter a
    988 	  situation in which recent store transactions to the L2 cache are lost
    989 	  and overwritten with stale memory contents from external memory. The
    990 	  workaround disables the write-allocate mode for the L2 cache via the
    991 	  ACTLR register. Note that setting specific bits in the ACTLR register
    992 	  may not be available in non-secure mode.
    993 
    994 config ARM_ERRATA_742230
    995 	bool "ARM errata: DMB operation may be faulty"
    996 	depends on CPU_V7 && SMP
    997 	depends on !ARCH_MULTIPLATFORM
    998 	help
    999 	  This option enables the workaround for the 742230 Cortex-A9
   1000 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
   1001 	  between two write operations may not ensure the correct visibility
   1002 	  ordering of the two writes. This workaround sets a specific bit in
   1003 	  the diagnostic register of the Cortex-A9 which causes the DMB
   1004 	  instruction to behave as a DSB, ensuring the correct behaviour of
   1005 	  the two writes.
   1006 
   1007 config ARM_ERRATA_742231
   1008 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
   1009 	depends on CPU_V7 && SMP
   1010 	depends on !ARCH_MULTIPLATFORM
   1011 	help
   1012 	  This option enables the workaround for the 742231 Cortex-A9
   1013 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
   1014 	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
   1015 	  accessing some data located in the same cache line, may get corrupted
   1016 	  data due to bad handling of the address hazard when the line gets
   1017 	  replaced from one of the CPUs at the same time as another CPU is
   1018 	  accessing it. This workaround sets specific bits in the diagnostic
   1019 	  register of the Cortex-A9 which reduces the linefill issuing
   1020 	  capabilities of the processor.
   1021 
   1022 config ARM_ERRATA_643719
   1023 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
   1024 	depends on CPU_V7 && SMP
   1025 	default y
   1026 	help
   1027 	  This option enables the workaround for the 643719 Cortex-A9 (prior to
   1028 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
   1029 	  register returns zero when it should return one. The workaround
   1030 	  corrects this value, ensuring cache maintenance operations which use
   1031 	  it behave as intended and avoiding data corruption.
   1032 
   1033 config ARM_ERRATA_720789
   1034 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
   1035 	depends on CPU_V7
   1036 	help
   1037 	  This option enables the workaround for the 720789 Cortex-A9 (prior to
   1038 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
   1039 	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
   1040 	  As a consequence of this erratum, some TLB entries which should be
   1041 	  invalidated are not, resulting in an incoherency in the system page
   1042 	  tables. The workaround changes the TLB flushing routines to invalidate
   1043 	  entries regardless of the ASID.
   1044 
   1045 config ARM_ERRATA_743622
   1046 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
   1047 	depends on CPU_V7
   1048 	depends on !ARCH_MULTIPLATFORM
   1049 	help
   1050 	  This option enables the workaround for the 743622 Cortex-A9
   1051 	  (r2p*) erratum. Under very rare conditions, a faulty
   1052 	  optimisation in the Cortex-A9 Store Buffer may lead to data
   1053 	  corruption. This workaround sets a specific bit in the diagnostic
   1054 	  register of the Cortex-A9 which disables the Store Buffer
   1055 	  optimisation, preventing the defect from occurring. This has no
   1056 	  visible impact on the overall performance or power consumption of the
   1057 	  processor.
   1058 
   1059 config ARM_ERRATA_751472
   1060 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
   1061 	depends on CPU_V7
   1062 	depends on !ARCH_MULTIPLATFORM
   1063 	help
   1064 	  This option enables the workaround for the 751472 Cortex-A9 (prior
   1065 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
   1066 	  completion of a following broadcasted operation if the second
   1067 	  operation is received by a CPU before the ICIALLUIS has completed,
   1068 	  potentially leading to corrupted entries in the cache or TLB.
   1069 
   1070 config ARM_ERRATA_754322
   1071 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
   1072 	depends on CPU_V7
   1073 	help
   1074 	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
   1075 	  r3p*) erratum. A speculative memory access may cause a page table walk
   1076 	  which starts prior to an ASID switch but completes afterwards. This
   1077 	  can populate the micro-TLB with a stale entry which may be hit with
   1078 	  the new ASID. This workaround places two dsb instructions in the mm
   1079 	  switching code so that no page table walks can cross the ASID switch.
   1080 
   1081 config ARM_ERRATA_754327
   1082 	bool "ARM errata: no automatic Store Buffer drain"
   1083 	depends on CPU_V7 && SMP
   1084 	help
   1085 	  This option enables the workaround for the 754327 Cortex-A9 (prior to
   1086 	  r2p0) erratum. The Store Buffer does not have any automatic draining
   1087 	  mechanism and therefore a livelock may occur if an external agent
   1088 	  continuously polls a memory location waiting to observe an update.
   1089 	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
   1090 	  written polling loops from denying visibility of updates to memory.
   1091 
   1092 config ARM_ERRATA_364296
   1093 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
   1094 	depends on CPU_V6
   1095 	help
   1096 	  This options enables the workaround for the 364296 ARM1136
   1097 	  r0p2 erratum (possible cache data corruption with
   1098 	  hit-under-miss enabled). It sets the undocumented bit 31 in
   1099 	  the auxiliary control register and the FI bit in the control
   1100 	  register, thus disabling hit-under-miss without putting the
   1101 	  processor into full low interrupt latency mode. ARM11MPCore
   1102 	  is not affected.
   1103 
   1104 config ARM_ERRATA_764369
   1105 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
   1106 	depends on CPU_V7 && SMP
   1107 	help
   1108 	  This option enables the workaround for erratum 764369
   1109 	  affecting Cortex-A9 MPCore with two or more processors (all
   1110 	  current revisions). Under certain timing circumstances, a data
   1111 	  cache line maintenance operation by MVA targeting an Inner
   1112 	  Shareable memory region may fail to proceed up to either the
   1113 	  Point of Coherency or to the Point of Unification of the
   1114 	  system. This workaround adds a DSB instruction before the
   1115 	  relevant cache maintenance functions and sets a specific bit
   1116 	  in the diagnostic control register of the SCU.
   1117 
   1118 config ARM_ERRATA_775420
   1119        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
   1120        depends on CPU_V7
   1121        help
   1122 	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
   1123 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
   1124 	 operation aborts with MMU exception, it might cause the processor
   1125 	 to deadlock. This workaround puts DSB before executing ISB if
   1126 	 an abort may occur on cache maintenance.
   1127 
   1128 config ARM_ERRATA_798181
   1129 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
   1130 	depends on CPU_V7 && SMP
   1131 	help
   1132 	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
   1133 	  adequately shooting down all use of the old entries. This
   1134 	  option enables the Linux kernel workaround for this erratum
   1135 	  which sends an IPI to the CPUs that are running the same ASID
   1136 	  as the one being invalidated.
   1137 
   1138 config ARM_ERRATA_773022
   1139 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
   1140 	depends on CPU_V7
   1141 	help
   1142 	  This option enables the workaround for the 773022 Cortex-A15
   1143 	  (up to r0p4) erratum. In certain rare sequences of code, the
   1144 	  loop buffer may deliver incorrect instructions. This
   1145 	  workaround disables the loop buffer to avoid the erratum.
   1146 
   1147 config ARM_ERRATA_818325_852422
   1148 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
   1149 	depends on CPU_V7
   1150 	help
   1151 	  This option enables the workaround for:
   1152 	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
   1153 	    instruction might deadlock.  Fixed in r0p1.
   1154 	  - Cortex-A12 852422: Execution of a sequence of instructions might
   1155 	    lead to either a data corruption or a CPU deadlock.  Not fixed in
   1156 	    any Cortex-A12 cores yet.
   1157 	  This workaround for all both errata involves setting bit[12] of the
   1158 	  Feature Register. This bit disables an optimisation applied to a
   1159 	  sequence of 2 instructions that use opposing condition codes.
   1160 
   1161 config ARM_ERRATA_821420
   1162 	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
   1163 	depends on CPU_V7
   1164 	help
   1165 	  This option enables the workaround for the 821420 Cortex-A12
   1166 	  (all revs) erratum. In very rare timing conditions, a sequence
   1167 	  of VMOV to Core registers instructions, for which the second
   1168 	  one is in the shadow of a branch or abort, can lead to a
   1169 	  deadlock when the VMOV instructions are issued out-of-order.
   1170 
   1171 config ARM_ERRATA_825619
   1172 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
   1173 	depends on CPU_V7
   1174 	help
   1175 	  This option enables the workaround for the 825619 Cortex-A12
   1176 	  (all revs) erratum. Within rare timing constraints, executing a
   1177 	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
   1178 	  and Device/Strongly-Ordered loads and stores might cause deadlock
   1179 
   1180 config ARM_ERRATA_852421
   1181 	bool "ARM errata: A17: DMB ST might fail to create order between stores"
   1182 	depends on CPU_V7
   1183 	help
   1184 	  This option enables the workaround for the 852421 Cortex-A17
   1185 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
   1186 	  execution of a DMB ST instruction might fail to properly order
   1187 	  stores from GroupA and stores from GroupB.
   1188 
   1189 config ARM_ERRATA_852423
   1190 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
   1191 	depends on CPU_V7
   1192 	help
   1193 	  This option enables the workaround for:
   1194 	  - Cortex-A17 852423: Execution of a sequence of instructions might
   1195 	    lead to either a data corruption or a CPU deadlock.  Not fixed in
   1196 	    any Cortex-A17 cores yet.
   1197 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
   1198 	  config option from the A12 erratum due to the way errata are checked
   1199 	  for and handled.
   1200 
   1201 endmenu
   1202 
   1203 source "arch/arm/common/Kconfig"
   1204 
   1205 menu "Bus support"
   1206 
   1207 config ISA
   1208 	bool
   1209 	help
   1210 	  Find out whether you have ISA slots on your motherboard.  ISA is the
   1211 	  name of a bus system, i.e. the way the CPU talks to the other stuff
   1212 	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
   1213 	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
   1214 	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
   1215 
   1216 # Select ISA DMA controller support
   1217 config ISA_DMA
   1218 	bool
   1219 	select ISA_DMA_API
   1220 
   1221 # Select ISA DMA interface
   1222 config ISA_DMA_API
   1223 	bool
   1224 
   1225 config PCI_NANOENGINE
   1226 	bool "BSE nanoEngine PCI support"
   1227 	depends on SA1100_NANOENGINE
   1228 	help
   1229 	  Enable PCI on the BSE nanoEngine board.
   1230 
   1231 config PCI_HOST_ITE8152
   1232 	bool
   1233 	depends on PCI && MACH_ARMCORE
   1234 	default y
   1235 	select DMABOUNCE
   1236 
   1237 endmenu
   1238 
   1239 menu "Kernel Features"
   1240 
   1241 config HAVE_SMP
   1242 	bool
   1243 	help
   1244 	  This option should be selected by machines which have an SMP-
   1245 	  capable CPU.
   1246 
   1247 	  The only effect of this option is to make the SMP-related
   1248 	  options available to the user for configuration.
   1249 
   1250 config SMP
   1251 	bool "Symmetric Multi-Processing"
   1252 	depends on CPU_V6K || CPU_V7
   1253 	depends on GENERIC_CLOCKEVENTS
   1254 	depends on HAVE_SMP
   1255 	depends on MMU || ARM_MPU
   1256 	select IRQ_WORK
   1257 	help
   1258 	  This enables support for systems with more than one CPU. If you have
   1259 	  a system with only one CPU, say N. If you have a system with more
   1260 	  than one CPU, say Y.
   1261 
   1262 	  If you say N here, the kernel will run on uni- and multiprocessor
   1263 	  machines, but will use only one CPU of a multiprocessor machine. If
   1264 	  you say Y here, the kernel will run on many, but not all,
   1265 	  uniprocessor machines. On a uniprocessor machine, the kernel
   1266 	  will run faster if you say N here.
   1267 
   1268 	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
   1269 	  <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
   1270 	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
   1271 
   1272 	  If you don't know what to do here, say N.
   1273 
   1274 config SMP_ON_UP
   1275 	bool "Allow booting SMP kernel on uniprocessor systems"
   1276 	depends on SMP && !XIP_KERNEL && MMU
   1277 	default y
   1278 	help
   1279 	  SMP kernels contain instructions which fail on non-SMP processors.
   1280 	  Enabling this option allows the kernel to modify itself to make
   1281 	  these instructions safe.  Disabling it allows about 1K of space
   1282 	  savings.
   1283 
   1284 	  If you don't know what to do here, say Y.
   1285 
   1286 config ARM_CPU_TOPOLOGY
   1287 	bool "Support cpu topology definition"
   1288 	depends on SMP && CPU_V7
   1289 	default y
   1290 	help
   1291 	  Support ARM cpu topology definition. The MPIDR register defines
   1292 	  affinity between processors which is then used to describe the cpu
   1293 	  topology of an ARM System.
   1294 
   1295 config SCHED_MC
   1296 	bool "Multi-core scheduler support"
   1297 	depends on ARM_CPU_TOPOLOGY
   1298 	help
   1299 	  Multi-core scheduler support improves the CPU scheduler's decision
   1300 	  making when dealing with multi-core CPU chips at a cost of slightly
   1301 	  increased overhead in some places. If unsure say N here.
   1302 
   1303 config SCHED_SMT
   1304 	bool "SMT scheduler support"
   1305 	depends on ARM_CPU_TOPOLOGY
   1306 	help
   1307 	  Improves the CPU scheduler's decision making when dealing with
   1308 	  MultiThreading at a cost of slightly increased overhead in some
   1309 	  places. If unsure say N here.
   1310 
   1311 config HAVE_ARM_SCU
   1312 	bool
   1313 	help
   1314 	  This option enables support for the ARM snoop control unit
   1315 
   1316 config HAVE_ARM_ARCH_TIMER
   1317 	bool "Architected timer support"
   1318 	depends on CPU_V7
   1319 	select ARM_ARCH_TIMER
   1320 	select GENERIC_CLOCKEVENTS
   1321 	help
   1322 	  This option enables support for the ARM architected timer
   1323 
   1324 config HAVE_ARM_TWD
   1325 	bool
   1326 	help
   1327 	  This options enables support for the ARM timer and watchdog unit
   1328 
   1329 config MCPM
   1330 	bool "Multi-Cluster Power Management"
   1331 	depends on CPU_V7 && SMP
   1332 	help
   1333 	  This option provides the common power management infrastructure
   1334 	  for (multi-)cluster based systems, such as big.LITTLE based
   1335 	  systems.
   1336 
   1337 config MCPM_QUAD_CLUSTER
   1338 	bool
   1339 	depends on MCPM
   1340 	help
   1341 	  To avoid wasting resources unnecessarily, MCPM only supports up
   1342 	  to 2 clusters by default.
   1343 	  Platforms with 3 or 4 clusters that use MCPM must select this
   1344 	  option to allow the additional clusters to be managed.
   1345 
   1346 config BIG_LITTLE
   1347 	bool "big.LITTLE support (Experimental)"
   1348 	depends on CPU_V7 && SMP
   1349 	select MCPM
   1350 	help
   1351 	  This option enables support selections for the big.LITTLE
   1352 	  system architecture.
   1353 
   1354 config BL_SWITCHER
   1355 	bool "big.LITTLE switcher support"
   1356 	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
   1357 	select CPU_PM
   1358 	help
   1359 	  The big.LITTLE "switcher" provides the core functionality to
   1360 	  transparently handle transition between a cluster of A15's
   1361 	  and a cluster of A7's in a big.LITTLE system.
   1362 
   1363 config BL_SWITCHER_DUMMY_IF
   1364 	tristate "Simple big.LITTLE switcher user interface"
   1365 	depends on BL_SWITCHER && DEBUG_KERNEL
   1366 	help
   1367 	  This is a simple and dummy char dev interface to control
   1368 	  the big.LITTLE switcher core code.  It is meant for
   1369 	  debugging purposes only.
   1370 
   1371 choice
   1372 	prompt "Memory split"
   1373 	depends on MMU
   1374 	default VMSPLIT_3G
   1375 	help
   1376 	  Select the desired split between kernel and user memory.
   1377 
   1378 	  If you are not absolutely sure what you are doing, leave this
   1379 	  option alone!
   1380 
   1381 	config VMSPLIT_3G
   1382 		bool "3G/1G user/kernel split"
   1383 	config VMSPLIT_3G_OPT
   1384 		depends on !ARM_LPAE
   1385 		bool "3G/1G user/kernel split (for full 1G low memory)"
   1386 	config VMSPLIT_2G
   1387 		bool "2G/2G user/kernel split"
   1388 	config VMSPLIT_1G
   1389 		bool "1G/3G user/kernel split"
   1390 endchoice
   1391 
   1392 config PAGE_OFFSET
   1393 	hex
   1394 	default PHYS_OFFSET if !MMU
   1395 	default 0x40000000 if VMSPLIT_1G
   1396 	default 0x80000000 if VMSPLIT_2G
   1397 	default 0xB0000000 if VMSPLIT_3G_OPT
   1398 	default 0xC0000000
   1399 
   1400 config NR_CPUS
   1401 	int "Maximum number of CPUs (2-32)"
   1402 	range 2 32
   1403 	depends on SMP
   1404 	default "4"
   1405 
   1406 config HOTPLUG_CPU
   1407 	bool "Support for hot-pluggable CPUs"
   1408 	depends on SMP
   1409 	select GENERIC_IRQ_MIGRATION
   1410 	help
   1411 	  Say Y here to experiment with turning CPUs off and on.  CPUs
   1412 	  can be controlled through /sys/devices/system/cpu.
   1413 
   1414 config ARM_PSCI
   1415 	bool "Support for the ARM Power State Coordination Interface (PSCI)"
   1416 	depends on HAVE_ARM_SMCCC
   1417 	select ARM_PSCI_FW
   1418 	help
   1419 	  Say Y here if you want Linux to communicate with system firmware
   1420 	  implementing the PSCI specification for CPU-centric power
   1421 	  management operations described in ARM document number ARM DEN
   1422 	  0022A ("Power State Coordination Interface System Software on
   1423 	  ARM processors").
   1424 
   1425 # The GPIO number here must be sorted by descending number. In case of
   1426 # a multiplatform kernel, we just want the highest value required by the
   1427 # selected platforms.
   1428 config ARCH_NR_GPIO
   1429 	int
   1430 	default 2048 if ARCH_SOCFPGA
   1431 	default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
   1432 		ARCH_ZYNQ
   1433 	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
   1434 		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
   1435 	default 416 if ARCH_SUNXI
   1436 	default 392 if ARCH_U8500
   1437 	default 352 if ARCH_VT8500
   1438 	default 288 if ARCH_ROCKCHIP
   1439 	default 264 if MACH_H4700
   1440 	default 0
   1441 	help
   1442 	  Maximum number of GPIOs in the system.
   1443 
   1444 	  If unsure, leave the default value.
   1445 
   1446 config HZ_FIXED
   1447 	int
   1448 	default 200 if ARCH_EBSA110
   1449 	default 128 if SOC_AT91RM9200
   1450 	default 0
   1451 
   1452 choice
   1453 	depends on HZ_FIXED = 0
   1454 	prompt "Timer frequency"
   1455 
   1456 config HZ_100
   1457 	bool "100 Hz"
   1458 
   1459 config HZ_200
   1460 	bool "200 Hz"
   1461 
   1462 config HZ_250
   1463 	bool "250 Hz"
   1464 
   1465 config HZ_300
   1466 	bool "300 Hz"
   1467 
   1468 config HZ_500
   1469 	bool "500 Hz"
   1470 
   1471 config HZ_1000
   1472 	bool "1000 Hz"
   1473 
   1474 endchoice
   1475 
   1476 config HZ
   1477 	int
   1478 	default HZ_FIXED if HZ_FIXED != 0
   1479 	default 100 if HZ_100
   1480 	default 200 if HZ_200
   1481 	default 250 if HZ_250
   1482 	default 300 if HZ_300
   1483 	default 500 if HZ_500
   1484 	default 1000
   1485 
   1486 config SCHED_HRTICK
   1487 	def_bool HIGH_RES_TIMERS
   1488 
   1489 config THUMB2_KERNEL
   1490 	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
   1491 	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
   1492 	default y if CPU_THUMBONLY
   1493 	select ARM_UNWIND
   1494 	help
   1495 	  By enabling this option, the kernel will be compiled in
   1496 	  Thumb-2 mode.
   1497 
   1498 	  If unsure, say N.
   1499 
   1500 config THUMB2_AVOID_R_ARM_THM_JUMP11
   1501 	bool "Work around buggy Thumb-2 short branch relocations in gas"
   1502 	depends on THUMB2_KERNEL && MODULES
   1503 	default y
   1504 	help
   1505 	  Various binutils versions can resolve Thumb-2 branches to
   1506 	  locally-defined, preemptible global symbols as short-range "b.n"
   1507 	  branch instructions.
   1508 
   1509 	  This is a problem, because there's no guarantee the final
   1510 	  destination of the symbol, or any candidate locations for a
   1511 	  trampoline, are within range of the branch.  For this reason, the
   1512 	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
   1513 	  relocation in modules at all, and it makes little sense to add
   1514 	  support.
   1515 
   1516 	  The symptom is that the kernel fails with an "unsupported
   1517 	  relocation" error when loading some modules.
   1518 
   1519 	  Until fixed tools are available, passing
   1520 	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
   1521 	  code which hits this problem, at the cost of a bit of extra runtime
   1522 	  stack usage in some cases.
   1523 
   1524 	  The problem is described in more detail at:
   1525 	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
   1526 
   1527 	  Only Thumb-2 kernels are affected.
   1528 
   1529 	  Unless you are sure your tools don't have this problem, say Y.
   1530 
   1531 config ARM_PATCH_IDIV
   1532 	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
   1533 	depends on CPU_32v7 && !XIP_KERNEL
   1534 	default y
   1535 	help
   1536 	  The ARM compiler inserts calls to __aeabi_idiv() and
   1537 	  __aeabi_uidiv() when it needs to perform division on signed
   1538 	  and unsigned integers. Some v7 CPUs have support for the sdiv
   1539 	  and udiv instructions that can be used to implement those
   1540 	  functions.
   1541 
   1542 	  Enabling this option allows the kernel to modify itself to
   1543 	  replace the first two instructions of these library functions
   1544 	  with the sdiv or udiv plus "bx lr" instructions when the CPU
   1545 	  it is running on supports them. Typically this will be faster
   1546 	  and less power intensive than running the original library
   1547 	  code to do integer division.
   1548 
   1549 config AEABI
   1550 	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
   1551 	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
   1552 	help
   1553 	  This option allows for the kernel to be compiled using the latest
   1554 	  ARM ABI (aka EABI).  This is only useful if you are using a user
   1555 	  space environment that is also compiled with EABI.
   1556 
   1557 	  Since there are major incompatibilities between the legacy ABI and
   1558 	  EABI, especially with regard to structure member alignment, this
   1559 	  option also changes the kernel syscall calling convention to
   1560 	  disambiguate both ABIs and allow for backward compatibility support
   1561 	  (selected with CONFIG_OABI_COMPAT).
   1562 
   1563 	  To use this you need GCC version 4.0.0 or later.
   1564 
   1565 config OABI_COMPAT
   1566 	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
   1567 	depends on AEABI && !THUMB2_KERNEL
   1568 	help
   1569 	  This option preserves the old syscall interface along with the
   1570 	  new (ARM EABI) one. It also provides a compatibility layer to
   1571 	  intercept syscalls that have structure arguments which layout
   1572 	  in memory differs between the legacy ABI and the new ARM EABI
   1573 	  (only for non "thumb" binaries). This option adds a tiny
   1574 	  overhead to all syscalls and produces a slightly larger kernel.
   1575 
   1576 	  The seccomp filter system will not be available when this is
   1577 	  selected, since there is no way yet to sensibly distinguish
   1578 	  between calling conventions during filtering.
   1579 
   1580 	  If you know you'll be using only pure EABI user space then you
   1581 	  can say N here. If this option is not selected and you attempt
   1582 	  to execute a legacy ABI binary then the result will be
   1583 	  UNPREDICTABLE (in fact it can be predicted that it won't work
   1584 	  at all). If in doubt say N.
   1585 
   1586 config ARCH_HAS_HOLES_MEMORYMODEL
   1587 	bool
   1588 
   1589 config ARCH_SPARSEMEM_ENABLE
   1590 	bool
   1591 
   1592 config ARCH_SPARSEMEM_DEFAULT
   1593 	def_bool ARCH_SPARSEMEM_ENABLE
   1594 
   1595 config ARCH_SELECT_MEMORY_MODEL
   1596 	def_bool ARCH_SPARSEMEM_ENABLE
   1597 
   1598 config HAVE_ARCH_PFN_VALID
   1599 	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
   1600 
   1601 config HAVE_GENERIC_GUP
   1602 	def_bool y
   1603 	depends on ARM_LPAE
   1604 
   1605 config HIGHMEM
   1606 	bool "High Memory Support"
   1607 	depends on MMU
   1608 	help
   1609 	  The address space of ARM processors is only 4 Gigabytes large
   1610 	  and it has to accommodate user address space, kernel address
   1611 	  space as well as some memory mapped IO. That means that, if you
   1612 	  have a large amount of physical memory and/or IO, not all of the
   1613 	  memory can be "permanently mapped" by the kernel. The physical
   1614 	  memory that is not permanently mapped is called "high memory".
   1615 
   1616 	  Depending on the selected kernel/user memory split, minimum
   1617 	  vmalloc space and actual amount of RAM, you may not need this
   1618 	  option which should result in a slightly faster kernel.
   1619 
   1620 	  If unsure, say n.
   1621 
   1622 config HIGHPTE
   1623 	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
   1624 	depends on HIGHMEM
   1625 	default y
   1626 	help
   1627 	  The VM uses one page of physical memory for each page table.
   1628 	  For systems with a lot of processes, this can use a lot of
   1629 	  precious low memory, eventually leading to low memory being
   1630 	  consumed by page tables.  Setting this option will allow
   1631 	  user-space 2nd level page tables to reside in high memory.
   1632 
   1633 config CPU_SW_DOMAIN_PAN
   1634 	bool "Enable use of CPU domains to implement privileged no-access"
   1635 	depends on MMU && !ARM_LPAE
   1636 	default y
   1637 	help
   1638 	  Increase kernel security by ensuring that normal kernel accesses
   1639 	  are unable to access userspace addresses.  This can help prevent
   1640 	  use-after-free bugs becoming an exploitable privilege escalation
   1641 	  by ensuring that magic values (such as LIST_POISON) will always
   1642 	  fault when dereferenced.
   1643 
   1644 	  CPUs with low-vector mappings use a best-efforts implementation.
   1645 	  Their lower 1MB needs to remain accessible for the vectors, but
   1646 	  the remainder of userspace will become appropriately inaccessible.
   1647 
   1648 config HW_PERF_EVENTS
   1649 	def_bool y
   1650 	depends on ARM_PMU
   1651 
   1652 config SYS_SUPPORTS_HUGETLBFS
   1653        def_bool y
   1654        depends on ARM_LPAE
   1655 
   1656 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
   1657        def_bool y
   1658        depends on ARM_LPAE
   1659 
   1660 config ARCH_WANT_GENERAL_HUGETLB
   1661 	def_bool y
   1662 
   1663 config ARM_MODULE_PLTS
   1664 	bool "Use PLTs to allow module memory to spill over into vmalloc area"
   1665 	depends on MODULES
   1666 	default y
   1667 	help
   1668 	  Allocate PLTs when loading modules so that jumps and calls whose
   1669 	  targets are too far away for their relative offsets to be encoded
   1670 	  in the instructions themselves can be bounced via veneers in the
   1671 	  module's PLT. This allows modules to be allocated in the generic
   1672 	  vmalloc area after the dedicated module memory area has been
   1673 	  exhausted. The modules will use slightly more memory, but after
   1674 	  rounding up to page size, the actual memory footprint is usually
   1675 	  the same.
   1676 
   1677 	  Disabling this is usually safe for small single-platform
   1678 	  configurations. If unsure, say y.
   1679 
   1680 config FORCE_MAX_ZONEORDER
   1681 	int "Maximum zone order"
   1682 	default "12" if SOC_AM33XX
   1683 	default "9" if SA1111 || ARCH_EFM32
   1684 	default "11"
   1685 	help
   1686 	  The kernel memory allocator divides physically contiguous memory
   1687 	  blocks into "zones", where each zone is a power of two number of
   1688 	  pages.  This option selects the largest power of two that the kernel
   1689 	  keeps in the memory allocator.  If you need to allocate very large
   1690 	  blocks of physically contiguous memory, then you may need to
   1691 	  increase this value.
   1692 
   1693 	  This config option is actually maximum order plus one. For example,
   1694 	  a value of 11 means that the largest free memory block is 2^10 pages.
   1695 
   1696 config ALIGNMENT_TRAP
   1697 	bool
   1698 	depends on CPU_CP15_MMU
   1699 	default y if !ARCH_EBSA110
   1700 	select HAVE_PROC_CPU if PROC_FS
   1701 	help
   1702 	  ARM processors cannot fetch/store information which is not
   1703 	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
   1704 	  address divisible by 4. On 32-bit ARM processors, these non-aligned
   1705 	  fetch/store instructions will be emulated in software if you say
   1706 	  here, which has a severe performance impact. This is necessary for
   1707 	  correct operation of some network protocols. With an IP-only
   1708 	  configuration it is safe to say N, otherwise say Y.
   1709 
   1710 config UACCESS_WITH_MEMCPY
   1711 	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
   1712 	depends on MMU
   1713 	default y if CPU_FEROCEON
   1714 	help
   1715 	  Implement faster copy_to_user and clear_user methods for CPU
   1716 	  cores where a 8-word STM instruction give significantly higher
   1717 	  memory write throughput than a sequence of individual 32bit stores.
   1718 
   1719 	  A possible side effect is a slight increase in scheduling latency
   1720 	  between threads sharing the same address space if they invoke
   1721 	  such copy operations with large buffers.
   1722 
   1723 	  However, if the CPU data cache is using a write-allocate mode,
   1724 	  this option is unlikely to provide any performance gain.
   1725 
   1726 config SECCOMP
   1727 	bool
   1728 	prompt "Enable seccomp to safely compute untrusted bytecode"
   1729 	---help---
   1730 	  This kernel feature is useful for number crunching applications
   1731 	  that may need to compute untrusted bytecode during their
   1732 	  execution. By using pipes or other transports made available to
   1733 	  the process as file descriptors supporting the read/write
   1734 	  syscalls, it's possible to isolate those applications in
   1735 	  their own address space using seccomp. Once seccomp is
   1736 	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
   1737 	  and the task is only allowed to execute a few safe syscalls
   1738 	  defined by each seccomp mode.
   1739 
   1740 config PARAVIRT
   1741 	bool "Enable paravirtualization code"
   1742 	help
   1743 	  This changes the kernel so it can modify itself when it is run
   1744 	  under a hypervisor, potentially improving performance significantly
   1745 	  over full virtualization.
   1746 
   1747 config PARAVIRT_TIME_ACCOUNTING
   1748 	bool "Paravirtual steal time accounting"
   1749 	select PARAVIRT
   1750 	help
   1751 	  Select this option to enable fine granularity task steal time
   1752 	  accounting. Time spent executing other tasks in parallel with
   1753 	  the current vCPU is discounted from the vCPU power. To account for
   1754 	  that, there can be a small performance impact.
   1755 
   1756 	  If in doubt, say N here.
   1757 
   1758 config XEN_DOM0
   1759 	def_bool y
   1760 	depends on XEN
   1761 
   1762 config XEN
   1763 	bool "Xen guest support on ARM"
   1764 	depends on ARM && AEABI && OF
   1765 	depends on CPU_V7 && !CPU_V6
   1766 	depends on !GENERIC_ATOMIC64
   1767 	depends on MMU
   1768 	select ARCH_DMA_ADDR_T_64BIT
   1769 	select ARM_PSCI
   1770 	select SWIOTLB
   1771 	select SWIOTLB_XEN
   1772 	select PARAVIRT
   1773 	help
   1774 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
   1775 
   1776 config STACKPROTECTOR_PER_TASK
   1777 	bool "Use a unique stack canary value for each task"
   1778 	depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
   1779 	select GCC_PLUGIN_ARM_SSP_PER_TASK
   1780 	default y
   1781 	help
   1782 	  Due to the fact that GCC uses an ordinary symbol reference from
   1783 	  which to load the value of the stack canary, this value can only
   1784 	  change at reboot time on SMP systems, and all tasks running in the
   1785 	  kernel's address space are forced to use the same canary value for
   1786 	  the entire duration that the system is up.
   1787 
   1788 	  Enable this option to switch to a different method that uses a
   1789 	  different canary value for each task.
   1790 
   1791 endmenu
   1792 
   1793 menu "Boot options"
   1794 
   1795 config USE_OF
   1796 	bool "Flattened Device Tree support"
   1797 	select IRQ_DOMAIN
   1798 	select OF
   1799 	help
   1800 	  Include support for flattened device tree machine descriptions.
   1801 
   1802 config ATAGS
   1803 	bool "Support for the traditional ATAGS boot data passing" if USE_OF
   1804 	default y
   1805 	help
   1806 	  This is the traditional way of passing data to the kernel at boot
   1807 	  time. If you are solely relying on the flattened device tree (or
   1808 	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
   1809 	  to remove ATAGS support from your kernel binary.  If unsure,
   1810 	  leave this to y.
   1811 
   1812 config DEPRECATED_PARAM_STRUCT
   1813 	bool "Provide old way to pass kernel parameters"
   1814 	depends on ATAGS
   1815 	help
   1816 	  This was deprecated in 2001 and announced to live on for 5 years.
   1817 	  Some old boot loaders still use this way.
   1818 
   1819 # Compressed boot loader in ROM.  Yes, we really want to ask about
   1820 # TEXT and BSS so we preserve their values in the config files.
   1821 config ZBOOT_ROM_TEXT
   1822 	hex "Compressed ROM boot loader base address"
   1823 	default "0"
   1824 	help
   1825 	  The physical address at which the ROM-able zImage is to be
   1826 	  placed in the target.  Platforms which normally make use of
   1827 	  ROM-able zImage formats normally set this to a suitable
   1828 	  value in their defconfig file.
   1829 
   1830 	  If ZBOOT_ROM is not enabled, this has no effect.
   1831 
   1832 config ZBOOT_ROM_BSS
   1833 	hex "Compressed ROM boot loader BSS address"
   1834 	default "0"
   1835 	help
   1836 	  The base address of an area of read/write memory in the target
   1837 	  for the ROM-able zImage which must be available while the
   1838 	  decompressor is running. It must be large enough to hold the
   1839 	  entire decompressed kernel plus an additional 128 KiB.
   1840 	  Platforms which normally make use of ROM-able zImage formats
   1841 	  normally set this to a suitable value in their defconfig file.
   1842 
   1843 	  If ZBOOT_ROM is not enabled, this has no effect.
   1844 
   1845 config ZBOOT_ROM
   1846 	bool "Compressed boot loader in ROM/flash"
   1847 	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
   1848 	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
   1849 	help
   1850 	  Say Y here if you intend to execute your compressed kernel image
   1851 	  (zImage) directly from ROM or flash.  If unsure, say N.
   1852 
   1853 config ARM_APPENDED_DTB
   1854 	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
   1855 	depends on OF
   1856 	help
   1857 	  With this option, the boot code will look for a device tree binary
   1858 	  (DTB) appended to zImage
   1859 	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
   1860 
   1861 	  This is meant as a backward compatibility convenience for those
   1862 	  systems with a bootloader that can't be upgraded to accommodate
   1863 	  the documented boot protocol using a device tree.
   1864 
   1865 	  Beware that there is very little in terms of protection against
   1866 	  this option being confused by leftover garbage in memory that might
   1867 	  look like a DTB header after a reboot if no actual DTB is appended
   1868 	  to zImage.  Do not leave this option active in a production kernel
   1869 	  if you don't intend to always append a DTB.  Proper passing of the
   1870 	  location into r2 of a bootloader provided DTB is always preferable
   1871 	  to this option.
   1872 
   1873 config ARM_ATAG_DTB_COMPAT
   1874 	bool "Supplement the appended DTB with traditional ATAG information"
   1875 	depends on ARM_APPENDED_DTB
   1876 	help
   1877 	  Some old bootloaders can't be updated to a DTB capable one, yet
   1878 	  they provide ATAGs with memory configuration, the ramdisk address,
   1879 	  the kernel cmdline string, etc.  Such information is dynamically
   1880 	  provided by the bootloader and can't always be stored in a static
   1881 	  DTB.  To allow a device tree enabled kernel to be used with such
   1882 	  bootloaders, this option allows zImage to extract the information
   1883 	  from the ATAG list and store it at run time into the appended DTB.
   1884 
   1885 choice
   1886 	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
   1887 	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
   1888 
   1889 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
   1890 	bool "Use bootloader kernel arguments if available"
   1891 	help
   1892 	  Uses the command-line options passed by the boot loader instead of
   1893 	  the device tree bootargs property. If the boot loader doesn't provide
   1894 	  any, the device tree bootargs property will be used.
   1895 
   1896 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
   1897 	bool "Extend with bootloader kernel arguments"
   1898 	help
   1899 	  The command-line arguments provided by the boot loader will be
   1900 	  appended to the the device tree bootargs property.
   1901 
   1902 endchoice
   1903 
   1904 config CMDLINE
   1905 	string "Default kernel command string"
   1906 	default ""
   1907 	help
   1908 	  On some architectures (EBSA110 and CATS), there is currently no way
   1909 	  for the boot loader to pass arguments to the kernel. For these
   1910 	  architectures, you should supply some command-line options at build
   1911 	  time by entering them here. As a minimum, you should specify the
   1912 	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
   1913 
   1914 choice
   1915 	prompt "Kernel command line type" if CMDLINE != ""
   1916 	default CMDLINE_FROM_BOOTLOADER
   1917 	depends on ATAGS
   1918 
   1919 config CMDLINE_FROM_BOOTLOADER
   1920 	bool "Use bootloader kernel arguments if available"
   1921 	help
   1922 	  Uses the command-line options passed by the boot loader. If
   1923 	  the boot loader doesn't provide any, the default kernel command
   1924 	  string provided in CMDLINE will be used.
   1925 
   1926 config CMDLINE_EXTEND
   1927 	bool "Extend bootloader kernel arguments"
   1928 	help
   1929 	  The command-line arguments provided by the boot loader will be
   1930 	  appended to the default kernel command string.
   1931 
   1932 config CMDLINE_FORCE
   1933 	bool "Always use the default kernel command string"
   1934 	help
   1935 	  Always use the default kernel command string, even if the boot
   1936 	  loader passes other arguments to the kernel.
   1937 	  This is useful if you cannot or don't want to change the
   1938 	  command-line options your boot loader passes to the kernel.
   1939 endchoice
   1940 
   1941 config XIP_KERNEL
   1942 	bool "Kernel Execute-In-Place from ROM"
   1943 	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
   1944 	help
   1945 	  Execute-In-Place allows the kernel to run from non-volatile storage
   1946 	  directly addressable by the CPU, such as NOR flash. This saves RAM
   1947 	  space since the text section of the kernel is not loaded from flash
   1948 	  to RAM.  Read-write sections, such as the data section and stack,
   1949 	  are still copied to RAM.  The XIP kernel is not compressed since
   1950 	  it has to run directly from flash, so it will take more space to
   1951 	  store it.  The flash address used to link the kernel object files,
   1952 	  and for storing it, is configuration dependent. Therefore, if you
   1953 	  say Y here, you must know the proper physical address where to
   1954 	  store the kernel image depending on your own flash memory usage.
   1955 
   1956 	  Also note that the make target becomes "make xipImage" rather than
   1957 	  "make zImage" or "make Image".  The final kernel binary to put in
   1958 	  ROM memory will be arch/arm/boot/xipImage.
   1959 
   1960 	  If unsure, say N.
   1961 
   1962 config XIP_PHYS_ADDR
   1963 	hex "XIP Kernel Physical Location"
   1964 	depends on XIP_KERNEL
   1965 	default "0x00080000"
   1966 	help
   1967 	  This is the physical address in your flash memory the kernel will
   1968 	  be linked for and stored to.  This address is dependent on your
   1969 	  own flash usage.
   1970 
   1971 config XIP_DEFLATED_DATA
   1972 	bool "Store kernel .data section compressed in ROM"
   1973 	depends on XIP_KERNEL
   1974 	select ZLIB_INFLATE
   1975 	help
   1976 	  Before the kernel is actually executed, its .data section has to be
   1977 	  copied to RAM from ROM. This option allows for storing that data
   1978 	  in compressed form and decompressed to RAM rather than merely being
   1979 	  copied, saving some precious ROM space. A possible drawback is a
   1980 	  slightly longer boot delay.
   1981 
   1982 config KEXEC
   1983 	bool "Kexec system call (EXPERIMENTAL)"
   1984 	depends on (!SMP || PM_SLEEP_SMP)
   1985 	depends on !CPU_V7M
   1986 	select KEXEC_CORE
   1987 	help
   1988 	  kexec is a system call that implements the ability to shutdown your
   1989 	  current kernel, and to start another kernel.  It is like a reboot
   1990 	  but it is independent of the system firmware.   And like a reboot
   1991 	  you can start any kernel with it, not just Linux.
   1992 
   1993 	  It is an ongoing process to be certain the hardware in a machine
   1994 	  is properly shutdown, so do not be surprised if this code does not
   1995 	  initially work for you.
   1996 
   1997 config ATAGS_PROC
   1998 	bool "Export atags in procfs"
   1999 	depends on ATAGS && KEXEC
   2000 	default y
   2001 	help
   2002 	  Should the atags used to boot the kernel be exported in an "atags"
   2003 	  file in procfs. Useful with kexec.
   2004 
   2005 config CRASH_DUMP
   2006 	bool "Build kdump crash kernel (EXPERIMENTAL)"
   2007 	help
   2008 	  Generate crash dump after being started by kexec. This should
   2009 	  be normally only set in special crash dump kernels which are
   2010 	  loaded in the main kernel with kexec-tools into a specially
   2011 	  reserved region and then later executed after a crash by
   2012 	  kdump/kexec. The crash dump kernel must be compiled to a
   2013 	  memory address not used by the main kernel
   2014 
   2015 	  For more details see Documentation/kdump/kdump.txt
   2016 
   2017 config AUTO_ZRELADDR
   2018 	bool "Auto calculation of the decompressed kernel image address"
   2019 	help
   2020 	  ZRELADDR is the physical address where the decompressed kernel
   2021 	  image will be placed. If AUTO_ZRELADDR is selected, the address
   2022 	  will be determined at run-time by masking the current IP with
   2023 	  0xf8000000. This assumes the zImage being placed in the first 128MB
   2024 	  from start of memory.
   2025 
   2026 config EFI_STUB
   2027 	bool
   2028 
   2029 config EFI
   2030 	bool "UEFI runtime support"
   2031 	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
   2032 	select UCS2_STRING
   2033 	select EFI_PARAMS_FROM_FDT
   2034 	select EFI_STUB
   2035 	select EFI_ARMSTUB
   2036 	select EFI_RUNTIME_WRAPPERS
   2037 	---help---
   2038 	  This option provides support for runtime services provided
   2039 	  by UEFI firmware (such as non-volatile variables, realtime
   2040 	  clock, and platform reset). A UEFI stub is also provided to
   2041 	  allow the kernel to be booted as an EFI application. This
   2042 	  is only useful for kernels that may run on systems that have
   2043 	  UEFI firmware.
   2044 
   2045 config DMI
   2046 	bool "Enable support for SMBIOS (DMI) tables"
   2047 	depends on EFI
   2048 	default y
   2049 	help
   2050 	  This enables SMBIOS/DMI feature for systems.
   2051 
   2052 	  This option is only useful on systems that have UEFI firmware.
   2053 	  However, even with this option, the resultant kernel should
   2054 	  continue to boot on existing non-UEFI platforms.
   2055 
   2056 	  NOTE: This does *NOT* enable or encourage the use of DMI quirks,
   2057 	  i.e., the the practice of identifying the platform via DMI to
   2058 	  decide whether certain workarounds for buggy hardware and/or
   2059 	  firmware need to be enabled. This would require the DMI subsystem
   2060 	  to be enabled much earlier than we do on ARM, which is non-trivial.
   2061 
   2062 endmenu
   2063 
   2064 menu "CPU Power Management"
   2065 
   2066 source "drivers/cpufreq/Kconfig"
   2067 
   2068 source "drivers/cpuidle/Kconfig"
   2069 
   2070 endmenu
   2071 
   2072 menu "Floating point emulation"
   2073 
   2074 comment "At least one emulation must be selected"
   2075 
   2076 config FPE_NWFPE
   2077 	bool "NWFPE math emulation"
   2078 	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
   2079 	---help---
   2080 	  Say Y to include the NWFPE floating point emulator in the kernel.
   2081 	  This is necessary to run most binaries. Linux does not currently
   2082 	  support floating point hardware so you need to say Y here even if
   2083 	  your machine has an FPA or floating point co-processor podule.
   2084 
   2085 	  You may say N here if you are going to load the Acorn FPEmulator
   2086 	  early in the bootup.
   2087 
   2088 config FPE_NWFPE_XP
   2089 	bool "Support extended precision"
   2090 	depends on FPE_NWFPE
   2091 	help
   2092 	  Say Y to include 80-bit support in the kernel floating-point
   2093 	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
   2094 	  Note that gcc does not generate 80-bit operations by default,
   2095 	  so in most cases this option only enlarges the size of the
   2096 	  floating point emulator without any good reason.
   2097 
   2098 	  You almost surely want to say N here.
   2099 
   2100 config FPE_FASTFPE
   2101 	bool "FastFPE math emulation (EXPERIMENTAL)"
   2102 	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
   2103 	---help---
   2104 	  Say Y here to include the FAST floating point emulator in the kernel.
   2105 	  This is an experimental much faster emulator which now also has full
   2106 	  precision for the mantissa.  It does not support any exceptions.
   2107 	  It is very simple, and approximately 3-6 times faster than NWFPE.
   2108 
   2109 	  It should be sufficient for most programs.  It may be not suitable
   2110 	  for scientific calculations, but you have to check this for yourself.
   2111 	  If you do not feel you need a faster FP emulation you should better
   2112 	  choose NWFPE.
   2113 
   2114 config VFP
   2115 	bool "VFP-format floating point maths"
   2116 	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
   2117 	help
   2118 	  Say Y to include VFP support code in the kernel. This is needed
   2119 	  if your hardware includes a VFP unit.
   2120 
   2121 	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
   2122 	  release notes and additional status information.
   2123 
   2124 	  Say N if your target does not have VFP hardware.
   2125 
   2126 config VFPv3
   2127 	bool
   2128 	depends on VFP
   2129 	default y if CPU_V7
   2130 
   2131 config NEON
   2132 	bool "Advanced SIMD (NEON) Extension support"
   2133 	depends on VFPv3 && CPU_V7
   2134 	help
   2135 	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
   2136 	  Extension.
   2137 
   2138 config KERNEL_MODE_NEON
   2139 	bool "Support for NEON in kernel mode"
   2140 	depends on NEON && AEABI
   2141 	help
   2142 	  Say Y to include support for NEON in kernel mode.
   2143 
   2144 endmenu
   2145 
   2146 menu "Power management options"
   2147 
   2148 source "kernel/power/Kconfig"
   2149 
   2150 config ARCH_SUSPEND_POSSIBLE
   2151 	depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
   2152 		CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
   2153 	def_bool y
   2154 
   2155 config ARM_CPU_SUSPEND
   2156 	def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
   2157 	depends on ARCH_SUSPEND_POSSIBLE
   2158 
   2159 config ARCH_HIBERNATION_POSSIBLE
   2160 	bool
   2161 	depends on MMU
   2162 	default y if ARCH_SUSPEND_POSSIBLE
   2163 
   2164 endmenu
   2165 
   2166 source "drivers/firmware/Kconfig"
   2167 
   2168 if CRYPTO
   2169 source "arch/arm/crypto/Kconfig"
   2170 endif
   2171 
   2172 source "arch/arm/kvm/Kconfig"