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pata_macio.c (40712B)


      1 /*
      2  * Libata based driver for Apple "macio" family of PATA controllers
      3  *
      4  * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
      5  *                     <benh@kernel.crashing.org>
      6  *
      7  * Some bits and pieces from drivers/ide/ppc/pmac.c
      8  *
      9  */
     10 
     11 #undef DEBUG
     12 #undef DEBUG_DMA
     13 
     14 #include <linux/kernel.h>
     15 #include <linux/module.h>
     16 #include <linux/init.h>
     17 #include <linux/blkdev.h>
     18 #include <linux/ata.h>
     19 #include <linux/libata.h>
     20 #include <linux/adb.h>
     21 #include <linux/pmu.h>
     22 #include <linux/scatterlist.h>
     23 #include <linux/of.h>
     24 #include <linux/gfp.h>
     25 #include <linux/pci.h>
     26 
     27 #include <scsi/scsi.h>
     28 #include <scsi/scsi_host.h>
     29 #include <scsi/scsi_device.h>
     30 
     31 #include <asm/macio.h>
     32 #include <asm/io.h>
     33 #include <asm/dbdma.h>
     34 #include <asm/machdep.h>
     35 #include <asm/pmac_feature.h>
     36 #include <asm/mediabay.h>
     37 
     38 #ifdef DEBUG_DMA
     39 #define dev_dbgdma(dev, format, arg...)		\
     40 	dev_printk(KERN_DEBUG , dev , format , ## arg)
     41 #else
     42 #define dev_dbgdma(dev, format, arg...)		\
     43 	({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
     44 #endif
     45 
     46 #define DRV_NAME	"pata_macio"
     47 #define DRV_VERSION	"0.9"
     48 
     49 /* Models of macio ATA controller */
     50 enum {
     51 	controller_ohare,	/* OHare based */
     52 	controller_heathrow,	/* Heathrow/Paddington */
     53 	controller_kl_ata3,	/* KeyLargo ATA-3 */
     54 	controller_kl_ata4,	/* KeyLargo ATA-4 */
     55 	controller_un_ata6,	/* UniNorth2 ATA-6 */
     56 	controller_k2_ata6,	/* K2 ATA-6 */
     57 	controller_sh_ata6,	/* Shasta ATA-6 */
     58 };
     59 
     60 static const char* macio_ata_names[] = {
     61 	"OHare ATA",		/* OHare based */
     62 	"Heathrow ATA",		/* Heathrow/Paddington */
     63 	"KeyLargo ATA-3",	/* KeyLargo ATA-3 (MDMA only) */
     64 	"KeyLargo ATA-4",	/* KeyLargo ATA-4 (UDMA/66) */
     65 	"UniNorth ATA-6",	/* UniNorth2 ATA-6 (UDMA/100) */
     66 	"K2 ATA-6",		/* K2 ATA-6 (UDMA/100) */
     67 	"Shasta ATA-6",		/* Shasta ATA-6 (UDMA/133) */
     68 };
     69 
     70 /*
     71  * Extra registers, both 32-bit little-endian
     72  */
     73 #define IDE_TIMING_CONFIG	0x200
     74 #define IDE_INTERRUPT		0x300
     75 
     76 /* Kauai (U2) ATA has different register setup */
     77 #define IDE_KAUAI_PIO_CONFIG	0x200
     78 #define IDE_KAUAI_ULTRA_CONFIG	0x210
     79 #define IDE_KAUAI_POLL_CONFIG	0x220
     80 
     81 /*
     82  * Timing configuration register definitions
     83  */
     84 
     85 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
     86 #define SYSCLK_TICKS(t)		(((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
     87 #define SYSCLK_TICKS_66(t)	(((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
     88 #define IDE_SYSCLK_NS		30	/* 33Mhz cell */
     89 #define IDE_SYSCLK_66_NS	15	/* 66Mhz cell */
     90 
     91 /* 133Mhz cell, found in shasta.
     92  * See comments about 100 Mhz Uninorth 2...
     93  * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
     94  * weird and I don't now why .. at this stage
     95  */
     96 #define TR_133_PIOREG_PIO_MASK		0xff000fff
     97 #define TR_133_PIOREG_MDMA_MASK		0x00fff800
     98 #define TR_133_UDMAREG_UDMA_MASK	0x0003ffff
     99 #define TR_133_UDMAREG_UDMA_EN		0x00000001
    100 
    101 /* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
    102  * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
    103  * controlled like gem or fw. It appears to be an evolution of keylargo
    104  * ATA4 with a timing register extended to 2x32bits registers (one
    105  * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
    106  * It has it's own local feature control register as well.
    107  *
    108  * After scratching my mind over the timing values, at least for PIO
    109  * and MDMA, I think I've figured the format of the timing register,
    110  * though I use pre-calculated tables for UDMA as usual...
    111  */
    112 #define TR_100_PIO_ADDRSETUP_MASK	0xff000000 /* Size of field unknown */
    113 #define TR_100_PIO_ADDRSETUP_SHIFT	24
    114 #define TR_100_MDMA_MASK		0x00fff000
    115 #define TR_100_MDMA_RECOVERY_MASK	0x00fc0000
    116 #define TR_100_MDMA_RECOVERY_SHIFT	18
    117 #define TR_100_MDMA_ACCESS_MASK		0x0003f000
    118 #define TR_100_MDMA_ACCESS_SHIFT	12
    119 #define TR_100_PIO_MASK			0xff000fff
    120 #define TR_100_PIO_RECOVERY_MASK	0x00000fc0
    121 #define TR_100_PIO_RECOVERY_SHIFT	6
    122 #define TR_100_PIO_ACCESS_MASK		0x0000003f
    123 #define TR_100_PIO_ACCESS_SHIFT		0
    124 
    125 #define TR_100_UDMAREG_UDMA_MASK	0x0000ffff
    126 #define TR_100_UDMAREG_UDMA_EN		0x00000001
    127 
    128 
    129 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
    130  * 40 connector cable and to 4 on 80 connector one.
    131  * Clock unit is 15ns (66Mhz)
    132  *
    133  * 3 Values can be programmed:
    134  *  - Write data setup, which appears to match the cycle time. They
    135  *    also call it DIOW setup.
    136  *  - Ready to pause time (from spec)
    137  *  - Address setup. That one is weird. I don't see where exactly
    138  *    it fits in UDMA cycles, I got it's name from an obscure piece
    139  *    of commented out code in Darwin. They leave it to 0, we do as
    140  *    well, despite a comment that would lead to think it has a
    141  *    min value of 45ns.
    142  * Apple also add 60ns to the write data setup (or cycle time ?) on
    143  * reads.
    144  */
    145 #define TR_66_UDMA_MASK			0xfff00000
    146 #define TR_66_UDMA_EN			0x00100000 /* Enable Ultra mode for DMA */
    147 #define TR_66_PIO_ADDRSETUP_MASK	0xe0000000 /* Address setup */
    148 #define TR_66_PIO_ADDRSETUP_SHIFT	29
    149 #define TR_66_UDMA_RDY2PAUS_MASK	0x1e000000 /* Ready 2 pause time */
    150 #define TR_66_UDMA_RDY2PAUS_SHIFT	25
    151 #define TR_66_UDMA_WRDATASETUP_MASK	0x01e00000 /* Write data setup time */
    152 #define TR_66_UDMA_WRDATASETUP_SHIFT	21
    153 #define TR_66_MDMA_MASK			0x000ffc00
    154 #define TR_66_MDMA_RECOVERY_MASK	0x000f8000
    155 #define TR_66_MDMA_RECOVERY_SHIFT	15
    156 #define TR_66_MDMA_ACCESS_MASK		0x00007c00
    157 #define TR_66_MDMA_ACCESS_SHIFT		10
    158 #define TR_66_PIO_MASK			0xe00003ff
    159 #define TR_66_PIO_RECOVERY_MASK		0x000003e0
    160 #define TR_66_PIO_RECOVERY_SHIFT	5
    161 #define TR_66_PIO_ACCESS_MASK		0x0000001f
    162 #define TR_66_PIO_ACCESS_SHIFT		0
    163 
    164 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
    165  * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
    166  *
    167  * The access time and recovery time can be programmed. Some older
    168  * Darwin code base limit OHare to 150ns cycle time. I decided to do
    169  * the same here fore safety against broken old hardware ;)
    170  * The HalfTick bit, when set, adds half a clock (15ns) to the access
    171  * time and removes one from recovery. It's not supported on KeyLargo
    172  * implementation afaik. The E bit appears to be set for PIO mode 0 and
    173  * is used to reach long timings used in this mode.
    174  */
    175 #define TR_33_MDMA_MASK			0x003ff800
    176 #define TR_33_MDMA_RECOVERY_MASK	0x001f0000
    177 #define TR_33_MDMA_RECOVERY_SHIFT	16
    178 #define TR_33_MDMA_ACCESS_MASK		0x0000f800
    179 #define TR_33_MDMA_ACCESS_SHIFT		11
    180 #define TR_33_MDMA_HALFTICK		0x00200000
    181 #define TR_33_PIO_MASK			0x000007ff
    182 #define TR_33_PIO_E			0x00000400
    183 #define TR_33_PIO_RECOVERY_MASK		0x000003e0
    184 #define TR_33_PIO_RECOVERY_SHIFT	5
    185 #define TR_33_PIO_ACCESS_MASK		0x0000001f
    186 #define TR_33_PIO_ACCESS_SHIFT		0
    187 
    188 /*
    189  * Interrupt register definitions. Only present on newer cells
    190  * (Keylargo and later afaik) so we don't use it.
    191  */
    192 #define IDE_INTR_DMA			0x80000000
    193 #define IDE_INTR_DEVICE			0x40000000
    194 
    195 /*
    196  * FCR Register on Kauai. Not sure what bit 0x4 is  ...
    197  */
    198 #define KAUAI_FCR_UATA_MAGIC		0x00000004
    199 #define KAUAI_FCR_UATA_RESET_N		0x00000002
    200 #define KAUAI_FCR_UATA_ENABLE		0x00000001
    201 
    202 
    203 /* Allow up to 256 DBDMA commands per xfer */
    204 #define MAX_DCMDS		256
    205 
    206 /* Don't let a DMA segment go all the way to 64K */
    207 #define MAX_DBDMA_SEG		0xff00
    208 
    209 
    210 /*
    211  * Wait 1s for disk to answer on IDE bus after a hard reset
    212  * of the device (via GPIO/FCR).
    213  *
    214  * Some devices seem to "pollute" the bus even after dropping
    215  * the BSY bit (typically some combo drives slave on the UDMA
    216  * bus) after a hard reset. Since we hard reset all drives on
    217  * KeyLargo ATA66, we have to keep that delay around. I may end
    218  * up not hard resetting anymore on these and keep the delay only
    219  * for older interfaces instead (we have to reset when coming
    220  * from MacOS...) --BenH.
    221  */
    222 #define IDE_WAKEUP_DELAY_MS	1000
    223 
    224 struct pata_macio_timing;
    225 
    226 struct pata_macio_priv {
    227 	int				kind;
    228 	int				aapl_bus_id;
    229 	int				mediabay : 1;
    230 	struct device_node		*node;
    231 	struct macio_dev		*mdev;
    232 	struct pci_dev			*pdev;
    233 	struct device			*dev;
    234 	int				irq;
    235 	u32				treg[2][2];
    236 	void __iomem			*tfregs;
    237 	void __iomem			*kauai_fcr;
    238 	struct dbdma_cmd *		dma_table_cpu;
    239 	dma_addr_t			dma_table_dma;
    240 	struct ata_host			*host;
    241 	const struct pata_macio_timing	*timings;
    242 };
    243 
    244 /* Previous variants of this driver used to calculate timings
    245  * for various variants of the chip and use tables for others.
    246  *
    247  * Not only was this confusing, but in addition, it isn't clear
    248  * whether our calculation code was correct. It didn't entirely
    249  * match the darwin code and whatever documentation I could find
    250  * on these cells
    251  *
    252  * I decided to entirely rely on a table instead for this version
    253  * of the driver. Also, because I don't really care about derated
    254  * modes and really old HW other than making it work, I'm not going
    255  * to calculate / snoop timing values for something else than the
    256  * standard modes.
    257  */
    258 struct pata_macio_timing {
    259 	int	mode;
    260 	u32	reg1;	/* Bits to set in first timing reg */
    261 	u32	reg2;	/* Bits to set in second timing reg */
    262 };
    263 
    264 static const struct pata_macio_timing pata_macio_ohare_timings[] = {
    265 	{ XFER_PIO_0,		0x00000526,	0, },
    266 	{ XFER_PIO_1,		0x00000085,	0, },
    267 	{ XFER_PIO_2,		0x00000025,	0, },
    268 	{ XFER_PIO_3,		0x00000025,	0, },
    269 	{ XFER_PIO_4,		0x00000025,	0, },
    270 	{ XFER_MW_DMA_0,	0x00074000,	0, },
    271 	{ XFER_MW_DMA_1,	0x00221000,	0, },
    272 	{ XFER_MW_DMA_2,	0x00211000,	0, },
    273 	{ -1, 0, 0 }
    274 };
    275 
    276 static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
    277 	{ XFER_PIO_0,		0x00000526,	0, },
    278 	{ XFER_PIO_1,		0x00000085,	0, },
    279 	{ XFER_PIO_2,		0x00000025,	0, },
    280 	{ XFER_PIO_3,		0x00000025,	0, },
    281 	{ XFER_PIO_4,		0x00000025,	0, },
    282 	{ XFER_MW_DMA_0,	0x00074000,	0, },
    283 	{ XFER_MW_DMA_1,	0x00221000,	0, },
    284 	{ XFER_MW_DMA_2,	0x00211000,	0, },
    285 	{ -1, 0, 0 }
    286 };
    287 
    288 static const struct pata_macio_timing pata_macio_kl33_timings[] = {
    289 	{ XFER_PIO_0,		0x00000526,	0, },
    290 	{ XFER_PIO_1,		0x00000085,	0, },
    291 	{ XFER_PIO_2,		0x00000025,	0, },
    292 	{ XFER_PIO_3,		0x00000025,	0, },
    293 	{ XFER_PIO_4,		0x00000025,	0, },
    294 	{ XFER_MW_DMA_0,	0x00084000,	0, },
    295 	{ XFER_MW_DMA_1,	0x00021800,	0, },
    296 	{ XFER_MW_DMA_2,	0x00011800,	0, },
    297 	{ -1, 0, 0 }
    298 };
    299 
    300 static const struct pata_macio_timing pata_macio_kl66_timings[] = {
    301 	{ XFER_PIO_0,		0x0000038c,	0, },
    302 	{ XFER_PIO_1,		0x0000020a,	0, },
    303 	{ XFER_PIO_2,		0x00000127,	0, },
    304 	{ XFER_PIO_3,		0x000000c6,	0, },
    305 	{ XFER_PIO_4,		0x00000065,	0, },
    306 	{ XFER_MW_DMA_0,	0x00084000,	0, },
    307 	{ XFER_MW_DMA_1,	0x00029800,	0, },
    308 	{ XFER_MW_DMA_2,	0x00019400,	0, },
    309 	{ XFER_UDMA_0,		0x19100000,	0, },
    310 	{ XFER_UDMA_1,		0x14d00000,	0, },
    311 	{ XFER_UDMA_2,		0x10900000,	0, },
    312 	{ XFER_UDMA_3,		0x0c700000,	0, },
    313 	{ XFER_UDMA_4,		0x0c500000,	0, },
    314 	{ -1, 0, 0 }
    315 };
    316 
    317 static const struct pata_macio_timing pata_macio_kauai_timings[] = {
    318 	{ XFER_PIO_0,		0x08000a92,	0, },
    319 	{ XFER_PIO_1,		0x0800060f,	0, },
    320 	{ XFER_PIO_2,		0x0800038b,	0, },
    321 	{ XFER_PIO_3,		0x05000249,	0, },
    322 	{ XFER_PIO_4,		0x04000148,	0, },
    323 	{ XFER_MW_DMA_0,	0x00618000,	0, },
    324 	{ XFER_MW_DMA_1,	0x00209000,	0, },
    325 	{ XFER_MW_DMA_2,	0x00148000,	0, },
    326 	{ XFER_UDMA_0,		         0,	0x000070c1, },
    327 	{ XFER_UDMA_1,		         0,	0x00005d81, },
    328 	{ XFER_UDMA_2,		         0,	0x00004a61, },
    329 	{ XFER_UDMA_3,		         0,	0x00003a51, },
    330 	{ XFER_UDMA_4,		         0,	0x00002a31, },
    331 	{ XFER_UDMA_5,		         0,	0x00002921, },
    332 	{ -1, 0, 0 }
    333 };
    334 
    335 static const struct pata_macio_timing pata_macio_shasta_timings[] = {
    336 	{ XFER_PIO_0,		0x0a000c97,	0, },
    337 	{ XFER_PIO_1,		0x07000712,	0, },
    338 	{ XFER_PIO_2,		0x040003cd,	0, },
    339 	{ XFER_PIO_3,		0x0500028b,	0, },
    340 	{ XFER_PIO_4,		0x0400010a,	0, },
    341 	{ XFER_MW_DMA_0,	0x00820800,	0, },
    342 	{ XFER_MW_DMA_1,	0x0028b000,	0, },
    343 	{ XFER_MW_DMA_2,	0x001ca000,	0, },
    344 	{ XFER_UDMA_0,		         0,	0x00035901, },
    345 	{ XFER_UDMA_1,		         0,	0x000348b1, },
    346 	{ XFER_UDMA_2,		         0,	0x00033881, },
    347 	{ XFER_UDMA_3,		         0,	0x00033861, },
    348 	{ XFER_UDMA_4,		         0,	0x00033841, },
    349 	{ XFER_UDMA_5,		         0,	0x00033031, },
    350 	{ XFER_UDMA_6,		         0,	0x00033021, },
    351 	{ -1, 0, 0 }
    352 };
    353 
    354 static const struct pata_macio_timing *pata_macio_find_timing(
    355 					    struct pata_macio_priv *priv,
    356 					    int mode)
    357 {
    358 	int i;
    359 
    360 	for (i = 0; priv->timings[i].mode > 0; i++) {
    361 		if (priv->timings[i].mode == mode)
    362 			return &priv->timings[i];
    363 	}
    364 	return NULL;
    365 }
    366 
    367 
    368 static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
    369 {
    370 	struct pata_macio_priv *priv = ap->private_data;
    371 	void __iomem *rbase = ap->ioaddr.cmd_addr;
    372 
    373 	if (priv->kind == controller_sh_ata6 ||
    374 	    priv->kind == controller_un_ata6 ||
    375 	    priv->kind == controller_k2_ata6) {
    376 		writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
    377 		writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
    378 	} else
    379 		writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
    380 }
    381 
    382 static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
    383 {
    384 	ata_sff_dev_select(ap, device);
    385 
    386 	/* Apply timings */
    387 	pata_macio_apply_timings(ap, device);
    388 }
    389 
    390 static void pata_macio_set_timings(struct ata_port *ap,
    391 				   struct ata_device *adev)
    392 {
    393 	struct pata_macio_priv *priv = ap->private_data;
    394 	const struct pata_macio_timing *t;
    395 
    396 	dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
    397 		adev->devno,
    398 		adev->pio_mode,
    399 		ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
    400 		adev->dma_mode,
    401 		ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
    402 
    403 	/* First clear timings */
    404 	priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
    405 
    406 	/* Now get the PIO timings */
    407 	t = pata_macio_find_timing(priv, adev->pio_mode);
    408 	if (t == NULL) {
    409 		dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
    410 			 adev->pio_mode);
    411 		t = pata_macio_find_timing(priv, XFER_PIO_0);
    412 	}
    413 	BUG_ON(t == NULL);
    414 
    415 	/* PIO timings only ever use the first treg */
    416 	priv->treg[adev->devno][0] |= t->reg1;
    417 
    418 	/* Now get DMA timings */
    419 	t = pata_macio_find_timing(priv, adev->dma_mode);
    420 	if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
    421 		dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
    422 		t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
    423 	}
    424 	BUG_ON(t == NULL);
    425 
    426 	/* DMA timings can use both tregs */
    427 	priv->treg[adev->devno][0] |= t->reg1;
    428 	priv->treg[adev->devno][1] |= t->reg2;
    429 
    430 	dev_dbg(priv->dev, " -> %08x %08x\n",
    431 		priv->treg[adev->devno][0],
    432 		priv->treg[adev->devno][1]);
    433 
    434 	/* Apply to hardware */
    435 	pata_macio_apply_timings(ap, adev->devno);
    436 }
    437 
    438 /*
    439  * Blast some well known "safe" values to the timing registers at init or
    440  * wakeup from sleep time, before we do real calculation
    441  */
    442 static void pata_macio_default_timings(struct pata_macio_priv *priv)
    443 {
    444 	unsigned int value, value2 = 0;
    445 
    446 	switch(priv->kind) {
    447 		case controller_sh_ata6:
    448 			value = 0x0a820c97;
    449 			value2 = 0x00033031;
    450 			break;
    451 		case controller_un_ata6:
    452 		case controller_k2_ata6:
    453 			value = 0x08618a92;
    454 			value2 = 0x00002921;
    455 			break;
    456 		case controller_kl_ata4:
    457 			value = 0x0008438c;
    458 			break;
    459 		case controller_kl_ata3:
    460 			value = 0x00084526;
    461 			break;
    462 		case controller_heathrow:
    463 		case controller_ohare:
    464 		default:
    465 			value = 0x00074526;
    466 			break;
    467 	}
    468 	priv->treg[0][0] = priv->treg[1][0] = value;
    469 	priv->treg[0][1] = priv->treg[1][1] = value2;
    470 }
    471 
    472 static int pata_macio_cable_detect(struct ata_port *ap)
    473 {
    474 	struct pata_macio_priv *priv = ap->private_data;
    475 
    476 	/* Get cable type from device-tree */
    477 	if (priv->kind == controller_kl_ata4 ||
    478 	    priv->kind == controller_un_ata6 ||
    479 	    priv->kind == controller_k2_ata6 ||
    480 	    priv->kind == controller_sh_ata6) {
    481 		const char* cable = of_get_property(priv->node, "cable-type",
    482 						    NULL);
    483 		struct device_node *root = of_find_node_by_path("/");
    484 		const char *model = of_get_property(root, "model", NULL);
    485 
    486 		of_node_put(root);
    487 
    488 		if (cable && !strncmp(cable, "80-", 3)) {
    489 			/* Some drives fail to detect 80c cable in PowerBook
    490 			 * These machine use proprietary short IDE cable
    491 			 * anyway
    492 			 */
    493 			if (!strncmp(model, "PowerBook", 9))
    494 				return ATA_CBL_PATA40_SHORT;
    495 			else
    496 				return ATA_CBL_PATA80;
    497 		}
    498 	}
    499 
    500 	/* G5's seem to have incorrect cable type in device-tree.
    501 	 * Let's assume they always have a 80 conductor cable, this seem to
    502 	 * be always the case unless the user mucked around
    503 	 */
    504 	if (of_device_is_compatible(priv->node, "K2-UATA") ||
    505 	    of_device_is_compatible(priv->node, "shasta-ata"))
    506 		return ATA_CBL_PATA80;
    507 
    508 	/* Anything else is 40 connectors */
    509 	return ATA_CBL_PATA40;
    510 }
    511 
    512 static void pata_macio_qc_prep(struct ata_queued_cmd *qc)
    513 {
    514 	unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
    515 	struct ata_port *ap = qc->ap;
    516 	struct pata_macio_priv *priv = ap->private_data;
    517 	struct scatterlist *sg;
    518 	struct dbdma_cmd *table;
    519 	unsigned int si, pi;
    520 
    521 	dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
    522 		   __func__, qc, qc->flags, write, qc->dev->devno);
    523 
    524 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
    525 		return;
    526 
    527 	table = (struct dbdma_cmd *) priv->dma_table_cpu;
    528 
    529 	pi = 0;
    530 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
    531 		u32 addr, sg_len, len;
    532 
    533 		/* determine if physical DMA addr spans 64K boundary.
    534 		 * Note h/w doesn't support 64-bit, so we unconditionally
    535 		 * truncate dma_addr_t to u32.
    536 		 */
    537 		addr = (u32) sg_dma_address(sg);
    538 		sg_len = sg_dma_len(sg);
    539 
    540 		while (sg_len) {
    541 			/* table overflow should never happen */
    542 			BUG_ON (pi++ >= MAX_DCMDS);
    543 
    544 			len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
    545 			table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);
    546 			table->req_count = cpu_to_le16(len);
    547 			table->phy_addr = cpu_to_le32(addr);
    548 			table->cmd_dep = 0;
    549 			table->xfer_status = 0;
    550 			table->res_count = 0;
    551 			addr += len;
    552 			sg_len -= len;
    553 			++table;
    554 		}
    555 	}
    556 
    557 	/* Should never happen according to Tejun */
    558 	BUG_ON(!pi);
    559 
    560 	/* Convert the last command to an input/output */
    561 	table--;
    562 	table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST);
    563 	table++;
    564 
    565 	/* Add the stop command to the end of the list */
    566 	memset(table, 0, sizeof(struct dbdma_cmd));
    567 	table->command = cpu_to_le16(DBDMA_STOP);
    568 
    569 	dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
    570 }
    571 
    572 
    573 static void pata_macio_freeze(struct ata_port *ap)
    574 {
    575 	struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
    576 
    577 	if (dma_regs) {
    578 		unsigned int timeout = 1000000;
    579 
    580 		/* Make sure DMA controller is stopped */
    581 		writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
    582 		while (--timeout && (readl(&dma_regs->status) & RUN))
    583 			udelay(1);
    584 	}
    585 
    586 	ata_sff_freeze(ap);
    587 }
    588 
    589 
    590 static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
    591 {
    592 	struct ata_port *ap = qc->ap;
    593 	struct pata_macio_priv *priv = ap->private_data;
    594 	struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
    595 	int dev = qc->dev->devno;
    596 
    597 	dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
    598 
    599 	/* Make sure DMA commands updates are visible */
    600 	writel(priv->dma_table_dma, &dma_regs->cmdptr);
    601 
    602 	/* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
    603 	 * UDMA reads
    604 	 */
    605 	if (priv->kind == controller_kl_ata4 &&
    606 	    (priv->treg[dev][0] & TR_66_UDMA_EN)) {
    607 		void __iomem *rbase = ap->ioaddr.cmd_addr;
    608 		u32 reg = priv->treg[dev][0];
    609 
    610 		if (!(qc->tf.flags & ATA_TFLAG_WRITE))
    611 			reg += 0x00800000;
    612 		writel(reg, rbase + IDE_TIMING_CONFIG);
    613 	}
    614 
    615 	/* issue r/w command */
    616 	ap->ops->sff_exec_command(ap, &qc->tf);
    617 }
    618 
    619 static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
    620 {
    621 	struct ata_port *ap = qc->ap;
    622 	struct pata_macio_priv *priv = ap->private_data;
    623 	struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
    624 
    625 	dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
    626 
    627 	writel((RUN << 16) | RUN, &dma_regs->control);
    628 	/* Make sure it gets to the controller right now */
    629 	(void)readl(&dma_regs->control);
    630 }
    631 
    632 static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
    633 {
    634 	struct ata_port *ap = qc->ap;
    635 	struct pata_macio_priv *priv = ap->private_data;
    636 	struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
    637 	unsigned int timeout = 1000000;
    638 
    639 	dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
    640 
    641 	/* Stop the DMA engine and wait for it to full halt */
    642 	writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
    643 	while (--timeout && (readl(&dma_regs->status) & RUN))
    644 		udelay(1);
    645 }
    646 
    647 static u8 pata_macio_bmdma_status(struct ata_port *ap)
    648 {
    649 	struct pata_macio_priv *priv = ap->private_data;
    650 	struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
    651 	u32 dstat, rstat = ATA_DMA_INTR;
    652 	unsigned long timeout = 0;
    653 
    654 	dstat = readl(&dma_regs->status);
    655 
    656 	dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
    657 
    658 	/* We have two things to deal with here:
    659 	 *
    660 	 * - The dbdma won't stop if the command was started
    661 	 * but completed with an error without transferring all
    662 	 * datas. This happens when bad blocks are met during
    663 	 * a multi-block transfer.
    664 	 *
    665 	 * - The dbdma fifo hasn't yet finished flushing to
    666 	 * to system memory when the disk interrupt occurs.
    667 	 *
    668 	 */
    669 
    670 	/* First check for errors */
    671 	if ((dstat & (RUN|DEAD)) != RUN)
    672 		rstat |= ATA_DMA_ERR;
    673 
    674 	/* If ACTIVE is cleared, the STOP command has been hit and
    675 	 * the transfer is complete. If not, we have to flush the
    676 	 * channel.
    677 	 */
    678 	if ((dstat & ACTIVE) == 0)
    679 		return rstat;
    680 
    681 	dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
    682 
    683 	/* If dbdma didn't execute the STOP command yet, the
    684 	 * active bit is still set. We consider that we aren't
    685 	 * sharing interrupts (which is hopefully the case with
    686 	 * those controllers) and so we just try to flush the
    687 	 * channel for pending data in the fifo
    688 	 */
    689 	udelay(1);
    690 	writel((FLUSH << 16) | FLUSH, &dma_regs->control);
    691 	for (;;) {
    692 		udelay(1);
    693 		dstat = readl(&dma_regs->status);
    694 		if ((dstat & FLUSH) == 0)
    695 			break;
    696 		if (++timeout > 1000) {
    697 			dev_warn(priv->dev, "timeout flushing DMA\n");
    698 			rstat |= ATA_DMA_ERR;
    699 			break;
    700 		}
    701 	}
    702 	return rstat;
    703 }
    704 
    705 /* port_start is when we allocate the DMA command list */
    706 static int pata_macio_port_start(struct ata_port *ap)
    707 {
    708 	struct pata_macio_priv *priv = ap->private_data;
    709 
    710 	if (ap->ioaddr.bmdma_addr == NULL)
    711 		return 0;
    712 
    713 	/* Allocate space for the DBDMA commands.
    714 	 *
    715 	 * The +2 is +1 for the stop command and +1 to allow for
    716 	 * aligning the start address to a multiple of 16 bytes.
    717 	 */
    718 	priv->dma_table_cpu =
    719 		dmam_alloc_coherent(priv->dev,
    720 				    (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
    721 				    &priv->dma_table_dma, GFP_KERNEL);
    722 	if (priv->dma_table_cpu == NULL) {
    723 		dev_err(priv->dev, "Unable to allocate DMA command list\n");
    724 		ap->ioaddr.bmdma_addr = NULL;
    725 		ap->mwdma_mask = 0;
    726 		ap->udma_mask = 0;
    727 	}
    728 	return 0;
    729 }
    730 
    731 static void pata_macio_irq_clear(struct ata_port *ap)
    732 {
    733 	struct pata_macio_priv *priv = ap->private_data;
    734 
    735 	/* Nothing to do here */
    736 
    737 	dev_dbgdma(priv->dev, "%s\n", __func__);
    738 }
    739 
    740 static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
    741 {
    742 	dev_dbg(priv->dev, "Enabling & resetting... \n");
    743 
    744 	if (priv->mediabay)
    745 		return;
    746 
    747 	if (priv->kind == controller_ohare && !resume) {
    748 		/* The code below is having trouble on some ohare machines
    749 		 * (timing related ?). Until I can put my hand on one of these
    750 		 * units, I keep the old way
    751 		 */
    752 		ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
    753 	} else {
    754 		int rc;
    755 
    756  		/* Reset and enable controller */
    757 		rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
    758 					 priv->node, priv->aapl_bus_id, 1);
    759 		ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
    760 				    priv->node, priv->aapl_bus_id, 1);
    761 		msleep(10);
    762 		/* Only bother waiting if there's a reset control */
    763 		if (rc == 0) {
    764 			ppc_md.feature_call(PMAC_FTR_IDE_RESET,
    765 					    priv->node, priv->aapl_bus_id, 0);
    766 			msleep(IDE_WAKEUP_DELAY_MS);
    767 		}
    768 	}
    769 
    770 	/* If resuming a PCI device, restore the config space here */
    771 	if (priv->pdev && resume) {
    772 		int rc;
    773 
    774 		pci_restore_state(priv->pdev);
    775 		rc = pcim_enable_device(priv->pdev);
    776 		if (rc)
    777 			dev_err(&priv->pdev->dev,
    778 				"Failed to enable device after resume (%d)\n",
    779 				rc);
    780 		else
    781 			pci_set_master(priv->pdev);
    782 	}
    783 
    784 	/* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
    785 	 * seem necessary and speeds up the boot process
    786 	 */
    787 	if (priv->kauai_fcr)
    788 		writel(KAUAI_FCR_UATA_MAGIC |
    789 		       KAUAI_FCR_UATA_RESET_N |
    790 		       KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
    791 }
    792 
    793 /* Hook the standard slave config to fixup some HW related alignment
    794  * restrictions
    795  */
    796 static int pata_macio_slave_config(struct scsi_device *sdev)
    797 {
    798 	struct ata_port *ap = ata_shost_to_port(sdev->host);
    799 	struct pata_macio_priv *priv = ap->private_data;
    800 	struct ata_device *dev;
    801 	u16 cmd;
    802 	int rc;
    803 
    804 	/* First call original */
    805 	rc = ata_scsi_slave_config(sdev);
    806 	if (rc)
    807 		return rc;
    808 
    809 	/* This is lifted from sata_nv */
    810 	dev = &ap->link.device[sdev->id];
    811 
    812 	/* OHare has issues with non cache aligned DMA on some chipsets */
    813 	if (priv->kind == controller_ohare) {
    814 		blk_queue_update_dma_alignment(sdev->request_queue, 31);
    815 		blk_queue_update_dma_pad(sdev->request_queue, 31);
    816 
    817 		/* Tell the world about it */
    818 		ata_dev_info(dev, "OHare alignment limits applied\n");
    819 		return 0;
    820 	}
    821 
    822 	/* We only have issues with ATAPI */
    823 	if (dev->class != ATA_DEV_ATAPI)
    824 		return 0;
    825 
    826 	/* Shasta and K2 seem to have "issues" with reads ... */
    827 	if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
    828 		/* Allright these are bad, apply restrictions */
    829 		blk_queue_update_dma_alignment(sdev->request_queue, 15);
    830 		blk_queue_update_dma_pad(sdev->request_queue, 15);
    831 
    832 		/* We enable MWI and hack cache line size directly here, this
    833 		 * is specific to this chipset and not normal values, we happen
    834 		 * to somewhat know what we are doing here (which is basically
    835 		 * to do the same Apple does and pray they did not get it wrong :-)
    836 		 */
    837 		BUG_ON(!priv->pdev);
    838 		pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
    839 		pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
    840 		pci_write_config_word(priv->pdev, PCI_COMMAND,
    841 				      cmd | PCI_COMMAND_INVALIDATE);
    842 
    843 		/* Tell the world about it */
    844 		ata_dev_info(dev, "K2/Shasta alignment limits applied\n");
    845 	}
    846 
    847 	return 0;
    848 }
    849 
    850 #ifdef CONFIG_PM_SLEEP
    851 static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
    852 {
    853 	int rc;
    854 
    855 	/* First, core libata suspend to do most of the work */
    856 	rc = ata_host_suspend(priv->host, mesg);
    857 	if (rc)
    858 		return rc;
    859 
    860 	/* Restore to default timings */
    861 	pata_macio_default_timings(priv);
    862 
    863 	/* Mask interrupt. Not strictly necessary but old driver did
    864 	 * it and I'd rather not change that here */
    865 	disable_irq(priv->irq);
    866 
    867 	/* The media bay will handle itself just fine */
    868 	if (priv->mediabay)
    869 		return 0;
    870 
    871 	/* Kauai has bus control FCRs directly here */
    872 	if (priv->kauai_fcr) {
    873 		u32 fcr = readl(priv->kauai_fcr);
    874 		fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
    875 		writel(fcr, priv->kauai_fcr);
    876 	}
    877 
    878 	/* For PCI, save state and disable DMA. No need to call
    879 	 * pci_set_power_state(), the HW doesn't do D states that
    880 	 * way, the platform code will take care of suspending the
    881 	 * ASIC properly
    882 	 */
    883 	if (priv->pdev) {
    884 		pci_save_state(priv->pdev);
    885 		pci_disable_device(priv->pdev);
    886 	}
    887 
    888 	/* Disable the bus on older machines and the cell on kauai */
    889 	ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
    890 			    priv->aapl_bus_id, 0);
    891 
    892 	return 0;
    893 }
    894 
    895 static int pata_macio_do_resume(struct pata_macio_priv *priv)
    896 {
    897 	/* Reset and re-enable the HW */
    898 	pata_macio_reset_hw(priv, 1);
    899 
    900 	/* Sanitize drive timings */
    901 	pata_macio_apply_timings(priv->host->ports[0], 0);
    902 
    903 	/* We want our IRQ back ! */
    904 	enable_irq(priv->irq);
    905 
    906 	/* Let the libata core take it from there */
    907 	ata_host_resume(priv->host);
    908 
    909 	return 0;
    910 }
    911 #endif /* CONFIG_PM_SLEEP */
    912 
    913 static struct scsi_host_template pata_macio_sht = {
    914 	ATA_BASE_SHT(DRV_NAME),
    915 	.sg_tablesize		= MAX_DCMDS,
    916 	/* We may not need that strict one */
    917 	.dma_boundary		= ATA_DMA_BOUNDARY,
    918 	/* Not sure what the real max is but we know it's less than 64K, let's
    919 	 * use 64K minus 256
    920 	 */
    921 	.max_segment_size	= MAX_DBDMA_SEG,
    922 	.slave_configure	= pata_macio_slave_config,
    923 };
    924 
    925 static struct ata_port_operations pata_macio_ops = {
    926 	.inherits		= &ata_bmdma_port_ops,
    927 
    928 	.freeze			= pata_macio_freeze,
    929 	.set_piomode		= pata_macio_set_timings,
    930 	.set_dmamode		= pata_macio_set_timings,
    931 	.cable_detect		= pata_macio_cable_detect,
    932 	.sff_dev_select		= pata_macio_dev_select,
    933 	.qc_prep		= pata_macio_qc_prep,
    934 	.bmdma_setup		= pata_macio_bmdma_setup,
    935 	.bmdma_start		= pata_macio_bmdma_start,
    936 	.bmdma_stop		= pata_macio_bmdma_stop,
    937 	.bmdma_status		= pata_macio_bmdma_status,
    938 	.port_start		= pata_macio_port_start,
    939 	.sff_irq_clear		= pata_macio_irq_clear,
    940 };
    941 
    942 static void pata_macio_invariants(struct pata_macio_priv *priv)
    943 {
    944 	const int *bidp;
    945 
    946 	/* Identify the type of controller */
    947 	if (of_device_is_compatible(priv->node, "shasta-ata")) {
    948 		priv->kind = controller_sh_ata6;
    949 	        priv->timings = pata_macio_shasta_timings;
    950 	} else if (of_device_is_compatible(priv->node, "kauai-ata")) {
    951 		priv->kind = controller_un_ata6;
    952 	        priv->timings = pata_macio_kauai_timings;
    953 	} else if (of_device_is_compatible(priv->node, "K2-UATA")) {
    954 		priv->kind = controller_k2_ata6;
    955 	        priv->timings = pata_macio_kauai_timings;
    956 	} else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
    957 		if (of_node_name_eq(priv->node, "ata-4")) {
    958 			priv->kind = controller_kl_ata4;
    959 			priv->timings = pata_macio_kl66_timings;
    960 		} else {
    961 			priv->kind = controller_kl_ata3;
    962 			priv->timings = pata_macio_kl33_timings;
    963 		}
    964 	} else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
    965 		priv->kind = controller_heathrow;
    966 		priv->timings = pata_macio_heathrow_timings;
    967 	} else {
    968 		priv->kind = controller_ohare;
    969 		priv->timings = pata_macio_ohare_timings;
    970 	}
    971 
    972 	/* XXX FIXME --- setup priv->mediabay here */
    973 
    974 	/* Get Apple bus ID (for clock and ASIC control) */
    975 	bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
    976 	priv->aapl_bus_id =  bidp ? *bidp : 0;
    977 
    978 	/* Fixup missing Apple bus ID in case of media-bay */
    979 	if (priv->mediabay && bidp == 0)
    980 		priv->aapl_bus_id = 1;
    981 }
    982 
    983 static void pata_macio_setup_ios(struct ata_ioports *ioaddr,
    984 				 void __iomem * base, void __iomem * dma)
    985 {
    986 	/* cmd_addr is the base of regs for that port */
    987 	ioaddr->cmd_addr	= base;
    988 
    989 	/* taskfile registers */
    990 	ioaddr->data_addr	= base + (ATA_REG_DATA    << 4);
    991 	ioaddr->error_addr	= base + (ATA_REG_ERR     << 4);
    992 	ioaddr->feature_addr	= base + (ATA_REG_FEATURE << 4);
    993 	ioaddr->nsect_addr	= base + (ATA_REG_NSECT   << 4);
    994 	ioaddr->lbal_addr	= base + (ATA_REG_LBAL    << 4);
    995 	ioaddr->lbam_addr	= base + (ATA_REG_LBAM    << 4);
    996 	ioaddr->lbah_addr	= base + (ATA_REG_LBAH    << 4);
    997 	ioaddr->device_addr	= base + (ATA_REG_DEVICE  << 4);
    998 	ioaddr->status_addr	= base + (ATA_REG_STATUS  << 4);
    999 	ioaddr->command_addr	= base + (ATA_REG_CMD     << 4);
   1000 	ioaddr->altstatus_addr	= base + 0x160;
   1001 	ioaddr->ctl_addr	= base + 0x160;
   1002 	ioaddr->bmdma_addr	= dma;
   1003 }
   1004 
   1005 static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
   1006 					 struct ata_port_info *pinfo)
   1007 {
   1008 	int i = 0;
   1009 
   1010 	pinfo->pio_mask		= 0;
   1011 	pinfo->mwdma_mask	= 0;
   1012 	pinfo->udma_mask	= 0;
   1013 
   1014 	while (priv->timings[i].mode > 0) {
   1015 		unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
   1016 		switch(priv->timings[i].mode & 0xf0) {
   1017 		case 0x00: /* PIO */
   1018 			pinfo->pio_mask |= (mask >> 8);
   1019 			break;
   1020 		case 0x20: /* MWDMA */
   1021 			pinfo->mwdma_mask |= mask;
   1022 			break;
   1023 		case 0x40: /* UDMA */
   1024 			pinfo->udma_mask |= mask;
   1025 			break;
   1026 		}
   1027 		i++;
   1028 	}
   1029 	dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
   1030 		pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
   1031 }
   1032 
   1033 static int pata_macio_common_init(struct pata_macio_priv *priv,
   1034 				  resource_size_t tfregs,
   1035 				  resource_size_t dmaregs,
   1036 				  resource_size_t fcregs,
   1037 				  unsigned long irq)
   1038 {
   1039 	struct ata_port_info		pinfo;
   1040 	const struct ata_port_info	*ppi[] = { &pinfo, NULL };
   1041 	void __iomem			*dma_regs = NULL;
   1042 
   1043 	/* Fill up privates with various invariants collected from the
   1044 	 * device-tree
   1045 	 */
   1046 	pata_macio_invariants(priv);
   1047 
   1048 	/* Make sure we have sane initial timings in the cache */
   1049 	pata_macio_default_timings(priv);
   1050 
   1051 	/* Allocate libata host for 1 port */
   1052 	memset(&pinfo, 0, sizeof(struct ata_port_info));
   1053 	pmac_macio_calc_timing_masks(priv, &pinfo);
   1054 	pinfo.flags		= ATA_FLAG_SLAVE_POSS;
   1055 	pinfo.port_ops		= &pata_macio_ops;
   1056 	pinfo.private_data	= priv;
   1057 
   1058 	priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
   1059 	if (priv->host == NULL) {
   1060 		dev_err(priv->dev, "Failed to allocate ATA port structure\n");
   1061 		return -ENOMEM;
   1062 	}
   1063 
   1064 	/* Setup the private data in host too */
   1065 	priv->host->private_data = priv;
   1066 
   1067 	/* Map base registers */
   1068 	priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
   1069 	if (priv->tfregs == NULL) {
   1070 		dev_err(priv->dev, "Failed to map ATA ports\n");
   1071 		return -ENOMEM;
   1072 	}
   1073 	priv->host->iomap = &priv->tfregs;
   1074 
   1075 	/* Map DMA regs */
   1076 	if (dmaregs != 0) {
   1077 		dma_regs = devm_ioremap(priv->dev, dmaregs,
   1078 					sizeof(struct dbdma_regs));
   1079 		if (dma_regs == NULL)
   1080 			dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
   1081 	}
   1082 
   1083 	/* If chip has local feature control, map those regs too */
   1084 	if (fcregs != 0) {
   1085 		priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
   1086 		if (priv->kauai_fcr == NULL) {
   1087 			dev_err(priv->dev, "Failed to map ATA FCR register\n");
   1088 			return -ENOMEM;
   1089 		}
   1090 	}
   1091 
   1092 	/* Setup port data structure */
   1093 	pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
   1094 			     priv->tfregs, dma_regs);
   1095 	priv->host->ports[0]->private_data = priv;
   1096 
   1097 	/* hard-reset the controller */
   1098 	pata_macio_reset_hw(priv, 0);
   1099 	pata_macio_apply_timings(priv->host->ports[0], 0);
   1100 
   1101 	/* Enable bus master if necessary */
   1102 	if (priv->pdev && dma_regs)
   1103 		pci_set_master(priv->pdev);
   1104 
   1105 	dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
   1106 		 macio_ata_names[priv->kind], priv->aapl_bus_id);
   1107 
   1108 	/* Start it up */
   1109 	priv->irq = irq;
   1110 	return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
   1111 				 &pata_macio_sht);
   1112 }
   1113 
   1114 static int pata_macio_attach(struct macio_dev *mdev,
   1115 			     const struct of_device_id *match)
   1116 {
   1117 	struct pata_macio_priv	*priv;
   1118 	resource_size_t		tfregs, dmaregs = 0;
   1119 	unsigned long		irq;
   1120 	int			rc;
   1121 
   1122 	/* Check for broken device-trees */
   1123 	if (macio_resource_count(mdev) == 0) {
   1124 		dev_err(&mdev->ofdev.dev,
   1125 			"No addresses for controller\n");
   1126 		return -ENXIO;
   1127 	}
   1128 
   1129 	/* Enable managed resources */
   1130 	macio_enable_devres(mdev);
   1131 
   1132 	/* Allocate and init private data structure */
   1133 	priv = devm_kzalloc(&mdev->ofdev.dev,
   1134 			    sizeof(struct pata_macio_priv), GFP_KERNEL);
   1135 	if (!priv)
   1136 		return -ENOMEM;
   1137 
   1138 	priv->node = of_node_get(mdev->ofdev.dev.of_node);
   1139 	priv->mdev = mdev;
   1140 	priv->dev = &mdev->ofdev.dev;
   1141 
   1142 	/* Request memory resource for taskfile registers */
   1143 	if (macio_request_resource(mdev, 0, "pata-macio")) {
   1144 		dev_err(&mdev->ofdev.dev,
   1145 			"Cannot obtain taskfile resource\n");
   1146 		return -EBUSY;
   1147 	}
   1148 	tfregs = macio_resource_start(mdev, 0);
   1149 
   1150 	/* Request resources for DMA registers if any */
   1151 	if (macio_resource_count(mdev) >= 2) {
   1152 		if (macio_request_resource(mdev, 1, "pata-macio-dma"))
   1153 			dev_err(&mdev->ofdev.dev,
   1154 				"Cannot obtain DMA resource\n");
   1155 		else
   1156 			dmaregs = macio_resource_start(mdev, 1);
   1157 	}
   1158 
   1159 	/*
   1160 	 * Fixup missing IRQ for some old implementations with broken
   1161 	 * device-trees.
   1162 	 *
   1163 	 * This is a bit bogus, it should be fixed in the device-tree itself,
   1164 	 * via the existing macio fixups, based on the type of interrupt
   1165 	 * controller in the machine. However, I have no test HW for this case,
   1166 	 * and this trick works well enough on those old machines...
   1167 	 */
   1168 	if (macio_irq_count(mdev) == 0) {
   1169 		dev_warn(&mdev->ofdev.dev,
   1170 			 "No interrupts for controller, using 13\n");
   1171 		irq = irq_create_mapping(NULL, 13);
   1172 	} else
   1173 		irq = macio_irq(mdev, 0);
   1174 
   1175 	/* Prevvent media bay callbacks until fully registered */
   1176 	lock_media_bay(priv->mdev->media_bay);
   1177 
   1178 	/* Get register addresses and call common initialization */
   1179 	rc = pata_macio_common_init(priv,
   1180 				    tfregs,		/* Taskfile regs */
   1181 				    dmaregs,		/* DBDMA regs */
   1182 				    0,			/* Feature control */
   1183 				    irq);
   1184 	unlock_media_bay(priv->mdev->media_bay);
   1185 
   1186 	return rc;
   1187 }
   1188 
   1189 static int pata_macio_detach(struct macio_dev *mdev)
   1190 {
   1191 	struct ata_host *host = macio_get_drvdata(mdev);
   1192 	struct pata_macio_priv *priv = host->private_data;
   1193 
   1194 	lock_media_bay(priv->mdev->media_bay);
   1195 
   1196 	/* Make sure the mediabay callback doesn't try to access
   1197 	 * dead stuff
   1198 	 */
   1199 	priv->host->private_data = NULL;
   1200 
   1201 	ata_host_detach(host);
   1202 
   1203 	unlock_media_bay(priv->mdev->media_bay);
   1204 
   1205 	return 0;
   1206 }
   1207 
   1208 #ifdef CONFIG_PM_SLEEP
   1209 static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
   1210 {
   1211 	struct ata_host *host = macio_get_drvdata(mdev);
   1212 
   1213 	return pata_macio_do_suspend(host->private_data, mesg);
   1214 }
   1215 
   1216 static int pata_macio_resume(struct macio_dev *mdev)
   1217 {
   1218 	struct ata_host *host = macio_get_drvdata(mdev);
   1219 
   1220 	return pata_macio_do_resume(host->private_data);
   1221 }
   1222 #endif /* CONFIG_PM_SLEEP */
   1223 
   1224 #ifdef CONFIG_PMAC_MEDIABAY
   1225 static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
   1226 {
   1227 	struct ata_host *host = macio_get_drvdata(mdev);
   1228 	struct ata_port *ap;
   1229 	struct ata_eh_info *ehi;
   1230 	struct ata_device *dev;
   1231 	unsigned long flags;
   1232 
   1233 	if (!host || !host->private_data)
   1234 		return;
   1235 	ap = host->ports[0];
   1236 	spin_lock_irqsave(ap->lock, flags);
   1237 	ehi = &ap->link.eh_info;
   1238 	if (mb_state == MB_CD) {
   1239 		ata_ehi_push_desc(ehi, "mediabay plug");
   1240 		ata_ehi_hotplugged(ehi);
   1241 		ata_port_freeze(ap);
   1242 	} else {
   1243 		ata_ehi_push_desc(ehi, "mediabay unplug");
   1244 		ata_for_each_dev(dev, &ap->link, ALL)
   1245 			dev->flags |= ATA_DFLAG_DETACH;
   1246 		ata_port_abort(ap);
   1247 	}
   1248 	spin_unlock_irqrestore(ap->lock, flags);
   1249 
   1250 }
   1251 #endif /* CONFIG_PMAC_MEDIABAY */
   1252 
   1253 
   1254 static int pata_macio_pci_attach(struct pci_dev *pdev,
   1255 				 const struct pci_device_id *id)
   1256 {
   1257 	struct pata_macio_priv	*priv;
   1258 	struct device_node	*np;
   1259 	resource_size_t		rbase;
   1260 
   1261 	/* We cannot use a MacIO controller without its OF device node */
   1262 	np = pci_device_to_OF_node(pdev);
   1263 	if (np == NULL) {
   1264 		dev_err(&pdev->dev,
   1265 			"Cannot find OF device node for controller\n");
   1266 		return -ENODEV;
   1267 	}
   1268 
   1269 	/* Check that it can be enabled */
   1270 	if (pcim_enable_device(pdev)) {
   1271 		dev_err(&pdev->dev,
   1272 			"Cannot enable controller PCI device\n");
   1273 		return -ENXIO;
   1274 	}
   1275 
   1276 	/* Allocate and init private data structure */
   1277 	priv = devm_kzalloc(&pdev->dev,
   1278 			    sizeof(struct pata_macio_priv), GFP_KERNEL);
   1279 	if (!priv)
   1280 		return -ENOMEM;
   1281 
   1282 	priv->node = of_node_get(np);
   1283 	priv->pdev = pdev;
   1284 	priv->dev = &pdev->dev;
   1285 
   1286 	/* Get MMIO regions */
   1287 	if (pci_request_regions(pdev, "pata-macio")) {
   1288 		dev_err(&pdev->dev,
   1289 			"Cannot obtain PCI resources\n");
   1290 		return -EBUSY;
   1291 	}
   1292 
   1293 	/* Get register addresses and call common initialization */
   1294 	rbase = pci_resource_start(pdev, 0);
   1295 	if (pata_macio_common_init(priv,
   1296 				   rbase + 0x2000,	/* Taskfile regs */
   1297 				   rbase + 0x1000,	/* DBDMA regs */
   1298 				   rbase,		/* Feature control */
   1299 				   pdev->irq))
   1300 		return -ENXIO;
   1301 
   1302 	return 0;
   1303 }
   1304 
   1305 static void pata_macio_pci_detach(struct pci_dev *pdev)
   1306 {
   1307 	struct ata_host *host = pci_get_drvdata(pdev);
   1308 
   1309 	ata_host_detach(host);
   1310 }
   1311 
   1312 #ifdef CONFIG_PM_SLEEP
   1313 static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
   1314 {
   1315 	struct ata_host *host = pci_get_drvdata(pdev);
   1316 
   1317 	return pata_macio_do_suspend(host->private_data, mesg);
   1318 }
   1319 
   1320 static int pata_macio_pci_resume(struct pci_dev *pdev)
   1321 {
   1322 	struct ata_host *host = pci_get_drvdata(pdev);
   1323 
   1324 	return pata_macio_do_resume(host->private_data);
   1325 }
   1326 #endif /* CONFIG_PM_SLEEP */
   1327 
   1328 static const struct of_device_id pata_macio_match[] =
   1329 {
   1330 	{
   1331 	.name 		= "IDE",
   1332 	},
   1333 	{
   1334 	.name 		= "ATA",
   1335 	},
   1336 	{
   1337 	.type		= "ide",
   1338 	},
   1339 	{
   1340 	.type		= "ata",
   1341 	},
   1342 	{},
   1343 };
   1344 MODULE_DEVICE_TABLE(of, pata_macio_match);
   1345 
   1346 static struct macio_driver pata_macio_driver =
   1347 {
   1348 	.driver = {
   1349 		.name 		= "pata-macio",
   1350 		.owner		= THIS_MODULE,
   1351 		.of_match_table	= pata_macio_match,
   1352 	},
   1353 	.probe		= pata_macio_attach,
   1354 	.remove		= pata_macio_detach,
   1355 #ifdef CONFIG_PM_SLEEP
   1356 	.suspend	= pata_macio_suspend,
   1357 	.resume		= pata_macio_resume,
   1358 #endif
   1359 #ifdef CONFIG_PMAC_MEDIABAY
   1360 	.mediabay_event	= pata_macio_mb_event,
   1361 #endif
   1362 };
   1363 
   1364 static const struct pci_device_id pata_macio_pci_match[] = {
   1365 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA),	0 },
   1366 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100),	0 },
   1367 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100),	0 },
   1368 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA),	0 },
   1369 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA),	0 },
   1370 	{},
   1371 };
   1372 
   1373 static struct pci_driver pata_macio_pci_driver = {
   1374 	.name		= "pata-pci-macio",
   1375 	.id_table	= pata_macio_pci_match,
   1376 	.probe		= pata_macio_pci_attach,
   1377 	.remove		= pata_macio_pci_detach,
   1378 #ifdef CONFIG_PM_SLEEP
   1379 	.suspend	= pata_macio_pci_suspend,
   1380 	.resume		= pata_macio_pci_resume,
   1381 #endif
   1382 	.driver = {
   1383 		.owner		= THIS_MODULE,
   1384 	},
   1385 };
   1386 MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
   1387 
   1388 
   1389 static int __init pata_macio_init(void)
   1390 {
   1391 	int rc;
   1392 
   1393 	if (!machine_is(powermac))
   1394 		return -ENODEV;
   1395 
   1396 	rc = pci_register_driver(&pata_macio_pci_driver);
   1397 	if (rc)
   1398 		return rc;
   1399 	rc = macio_register_driver(&pata_macio_driver);
   1400 	if (rc) {
   1401 		pci_unregister_driver(&pata_macio_pci_driver);
   1402 		return rc;
   1403 	}
   1404 	return 0;
   1405 }
   1406 
   1407 static void __exit pata_macio_exit(void)
   1408 {
   1409 	macio_unregister_driver(&pata_macio_driver);
   1410 	pci_unregister_driver(&pata_macio_pci_driver);
   1411 }
   1412 
   1413 module_init(pata_macio_init);
   1414 module_exit(pata_macio_exit);
   1415 
   1416 MODULE_AUTHOR("Benjamin Herrenschmidt");
   1417 MODULE_DESCRIPTION("Apple MacIO PATA driver");
   1418 MODULE_LICENSE("GPL");
   1419 MODULE_VERSION(DRV_VERSION);