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lan743x_main.h (27427B)


      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /* Copyright (C) 2018 Microchip Technology Inc. */
      3 
      4 #ifndef _LAN743X_H
      5 #define _LAN743X_H
      6 
      7 #include "lan743x_ptp.h"
      8 
      9 #define DRIVER_AUTHOR   "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
     10 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
     11 #define DRIVER_NAME "lan743x"
     12 
     13 /* Register Definitions */
     14 #define ID_REV				(0x00)
     15 #define ID_REV_ID_MASK_			(0xFFFF0000)
     16 #define ID_REV_ID_LAN7430_		(0x74300000)
     17 #define ID_REV_ID_LAN7431_		(0x74310000)
     18 #define ID_REV_IS_VALID_CHIP_ID_(id_rev)	\
     19 	(((id_rev) & 0xFFF00000) == 0x74300000)
     20 #define ID_REV_CHIP_REV_MASK_		(0x0000FFFF)
     21 #define ID_REV_CHIP_REV_A0_		(0x00000000)
     22 #define ID_REV_CHIP_REV_B0_		(0x00000010)
     23 
     24 #define FPGA_REV			(0x04)
     25 #define FPGA_REV_GET_MINOR_(fpga_rev)	(((fpga_rev) >> 8) & 0x000000FF)
     26 #define FPGA_REV_GET_MAJOR_(fpga_rev)	((fpga_rev) & 0x000000FF)
     27 
     28 #define HW_CFG					(0x010)
     29 #define HW_CFG_RELOAD_TYPE_ALL_			(0x00000FC0)
     30 #define HW_CFG_EE_OTP_RELOAD_			BIT(4)
     31 #define HW_CFG_LRST_				BIT(1)
     32 
     33 #define PMT_CTL					(0x014)
     34 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_		BIT(27)
     35 #define PMT_CTL_MAC_D3_RX_CLK_OVR_		BIT(25)
     36 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_		BIT(24)
     37 #define PMT_CTL_ETH_PHY_D3_OVR_			BIT(23)
     38 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_		BIT(18)
     39 #define PMT_CTL_GPIO_WAKEUP_EN_			BIT(15)
     40 #define PMT_CTL_EEE_WAKEUP_EN_			BIT(13)
     41 #define PMT_CTL_READY_				BIT(7)
     42 #define PMT_CTL_ETH_PHY_RST_			BIT(4)
     43 #define PMT_CTL_WOL_EN_				BIT(3)
     44 #define PMT_CTL_ETH_PHY_WAKE_EN_		BIT(2)
     45 #define PMT_CTL_WUPS_MASK_			(0x00000003)
     46 
     47 #define DP_SEL				(0x024)
     48 #define DP_SEL_DPRDY_			BIT(31)
     49 #define DP_SEL_MASK_			(0x0000001F)
     50 #define DP_SEL_RFE_RAM			(0x00000001)
     51 
     52 #define DP_SEL_VHF_HASH_LEN		(16)
     53 #define DP_SEL_VHF_VLAN_LEN		(128)
     54 
     55 #define DP_CMD				(0x028)
     56 #define DP_CMD_WRITE_			(0x00000001)
     57 
     58 #define DP_ADDR				(0x02C)
     59 
     60 #define DP_DATA_0			(0x030)
     61 
     62 #define E2P_CMD				(0x040)
     63 #define E2P_CMD_EPC_BUSY_		BIT(31)
     64 #define E2P_CMD_EPC_CMD_WRITE_		(0x30000000)
     65 #define E2P_CMD_EPC_CMD_EWEN_		(0x20000000)
     66 #define E2P_CMD_EPC_CMD_READ_		(0x00000000)
     67 #define E2P_CMD_EPC_TIMEOUT_		BIT(10)
     68 #define E2P_CMD_EPC_ADDR_MASK_		(0x000001FF)
     69 
     70 #define E2P_DATA			(0x044)
     71 
     72 #define GPIO_CFG0			(0x050)
     73 #define GPIO_CFG0_GPIO_DIR_BIT_(bit)	BIT(16 + (bit))
     74 #define GPIO_CFG0_GPIO_DATA_BIT_(bit)	BIT(0 + (bit))
     75 
     76 #define GPIO_CFG1			(0x054)
     77 #define GPIO_CFG1_GPIOEN_BIT_(bit)	BIT(16 + (bit))
     78 #define GPIO_CFG1_GPIOBUF_BIT_(bit)	BIT(0 + (bit))
     79 
     80 #define GPIO_CFG2			(0x058)
     81 #define GPIO_CFG2_1588_POL_BIT_(bit)	BIT(0 + (bit))
     82 
     83 #define GPIO_CFG3			(0x05C)
     84 #define GPIO_CFG3_1588_CH_SEL_BIT_(bit)	BIT(16 + (bit))
     85 #define GPIO_CFG3_1588_OE_BIT_(bit)	BIT(0 + (bit))
     86 
     87 #define FCT_RX_CTL			(0xAC)
     88 #define FCT_RX_CTL_EN_(channel)		BIT(28 + (channel))
     89 #define FCT_RX_CTL_DIS_(channel)	BIT(24 + (channel))
     90 #define FCT_RX_CTL_RESET_(channel)	BIT(20 + (channel))
     91 
     92 #define FCT_TX_CTL			(0xC4)
     93 #define FCT_TX_CTL_EN_(channel)		BIT(28 + (channel))
     94 #define FCT_TX_CTL_DIS_(channel)	BIT(24 + (channel))
     95 #define FCT_TX_CTL_RESET_(channel)	BIT(20 + (channel))
     96 
     97 #define FCT_FLOW(rx_channel)			(0xE0 + ((rx_channel) << 2))
     98 #define FCT_FLOW_CTL_OFF_THRESHOLD_		(0x00007F00)
     99 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value)	\
    100 	((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
    101 #define FCT_FLOW_CTL_REQ_EN_			BIT(7)
    102 #define FCT_FLOW_CTL_ON_THRESHOLD_		(0x0000007F)
    103 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value)	\
    104 	((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
    105 
    106 #define MAC_CR				(0x100)
    107 #define MAC_CR_EEE_EN_			BIT(17)
    108 #define MAC_CR_ADD_			BIT(12)
    109 #define MAC_CR_ASD_			BIT(11)
    110 #define MAC_CR_CNTR_RST_		BIT(5)
    111 #define MAC_CR_RST_			BIT(0)
    112 
    113 #define MAC_RX				(0x104)
    114 #define MAC_RX_MAX_SIZE_SHIFT_		(16)
    115 #define MAC_RX_MAX_SIZE_MASK_		(0x3FFF0000)
    116 #define MAC_RX_RXD_			BIT(1)
    117 #define MAC_RX_RXEN_			BIT(0)
    118 
    119 #define MAC_TX				(0x108)
    120 #define MAC_TX_TXD_			BIT(1)
    121 #define MAC_TX_TXEN_			BIT(0)
    122 
    123 #define MAC_FLOW			(0x10C)
    124 #define MAC_FLOW_CR_TX_FCEN_		BIT(30)
    125 #define MAC_FLOW_CR_RX_FCEN_		BIT(29)
    126 #define MAC_FLOW_CR_FCPT_MASK_		(0x0000FFFF)
    127 
    128 #define MAC_RX_ADDRH			(0x118)
    129 
    130 #define MAC_RX_ADDRL			(0x11C)
    131 
    132 #define MAC_MII_ACC			(0x120)
    133 #define MAC_MII_ACC_PHY_ADDR_SHIFT_	(11)
    134 #define MAC_MII_ACC_PHY_ADDR_MASK_	(0x0000F800)
    135 #define MAC_MII_ACC_MIIRINDA_SHIFT_	(6)
    136 #define MAC_MII_ACC_MIIRINDA_MASK_	(0x000007C0)
    137 #define MAC_MII_ACC_MII_READ_		(0x00000000)
    138 #define MAC_MII_ACC_MII_WRITE_		(0x00000002)
    139 #define MAC_MII_ACC_MII_BUSY_		BIT(0)
    140 
    141 #define MAC_MII_DATA			(0x124)
    142 
    143 #define MAC_EEE_TX_LPI_REQ_DLY_CNT		(0x130)
    144 
    145 #define MAC_WUCSR				(0x140)
    146 #define MAC_WUCSR_RFE_WAKE_EN_			BIT(14)
    147 #define MAC_WUCSR_PFDA_EN_			BIT(3)
    148 #define MAC_WUCSR_WAKE_EN_			BIT(2)
    149 #define MAC_WUCSR_MPEN_				BIT(1)
    150 #define MAC_WUCSR_BCST_EN_			BIT(0)
    151 
    152 #define MAC_WK_SRC				(0x144)
    153 
    154 #define MAC_WUF_CFG0			(0x150)
    155 #define MAC_NUM_OF_WUF_CFG		(32)
    156 #define MAC_WUF_CFG_BEGIN		(MAC_WUF_CFG0)
    157 #define MAC_WUF_CFG(index)		(MAC_WUF_CFG_BEGIN + (4 * (index)))
    158 #define MAC_WUF_CFG_EN_			BIT(31)
    159 #define MAC_WUF_CFG_TYPE_MCAST_		(0x02000000)
    160 #define MAC_WUF_CFG_TYPE_ALL_		(0x01000000)
    161 #define MAC_WUF_CFG_OFFSET_SHIFT_	(16)
    162 #define MAC_WUF_CFG_CRC16_MASK_		(0x0000FFFF)
    163 
    164 #define MAC_WUF_MASK0_0			(0x200)
    165 #define MAC_WUF_MASK0_1			(0x204)
    166 #define MAC_WUF_MASK0_2			(0x208)
    167 #define MAC_WUF_MASK0_3			(0x20C)
    168 #define MAC_WUF_MASK0_BEGIN		(MAC_WUF_MASK0_0)
    169 #define MAC_WUF_MASK1_BEGIN		(MAC_WUF_MASK0_1)
    170 #define MAC_WUF_MASK2_BEGIN		(MAC_WUF_MASK0_2)
    171 #define MAC_WUF_MASK3_BEGIN		(MAC_WUF_MASK0_3)
    172 #define MAC_WUF_MASK0(index)		(MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
    173 #define MAC_WUF_MASK1(index)		(MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
    174 #define MAC_WUF_MASK2(index)		(MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
    175 #define MAC_WUF_MASK3(index)		(MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
    176 
    177 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
    178 #define RFE_ADDR_FILT_HI(x)		(0x400 + (8 * (x)))
    179 #define RFE_ADDR_FILT_HI_VALID_		BIT(31)
    180 
    181 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
    182 #define RFE_ADDR_FILT_LO(x)		(0x404 + (8 * (x)))
    183 
    184 #define RFE_CTL				(0x508)
    185 #define RFE_CTL_AB_			BIT(10)
    186 #define RFE_CTL_AM_			BIT(9)
    187 #define RFE_CTL_AU_			BIT(8)
    188 #define RFE_CTL_MCAST_HASH_		BIT(3)
    189 #define RFE_CTL_DA_PERFECT_		BIT(1)
    190 
    191 #define RFE_RSS_CFG			(0x554)
    192 #define RFE_RSS_CFG_UDP_IPV6_EX_	BIT(16)
    193 #define RFE_RSS_CFG_TCP_IPV6_EX_	BIT(15)
    194 #define RFE_RSS_CFG_IPV6_EX_		BIT(14)
    195 #define RFE_RSS_CFG_UDP_IPV6_		BIT(13)
    196 #define RFE_RSS_CFG_TCP_IPV6_		BIT(12)
    197 #define RFE_RSS_CFG_IPV6_		BIT(11)
    198 #define RFE_RSS_CFG_UDP_IPV4_		BIT(10)
    199 #define RFE_RSS_CFG_TCP_IPV4_		BIT(9)
    200 #define RFE_RSS_CFG_IPV4_		BIT(8)
    201 #define RFE_RSS_CFG_VALID_HASH_BITS_	(0x000000E0)
    202 #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_	BIT(2)
    203 #define RFE_RSS_CFG_RSS_HASH_STORE_	BIT(1)
    204 #define RFE_RSS_CFG_RSS_ENABLE_		BIT(0)
    205 
    206 #define RFE_HASH_KEY(index)		(0x558 + (index << 2))
    207 
    208 #define RFE_INDX(index)			(0x580 + (index << 2))
    209 
    210 #define MAC_WUCSR2			(0x600)
    211 
    212 #define INT_STS				(0x780)
    213 #define INT_BIT_DMA_RX_(channel)	BIT(24 + (channel))
    214 #define INT_BIT_ALL_RX_			(0x0F000000)
    215 #define INT_BIT_DMA_TX_(channel)	BIT(16 + (channel))
    216 #define INT_BIT_ALL_TX_			(0x000F0000)
    217 #define INT_BIT_SW_GP_			BIT(9)
    218 #define INT_BIT_1588_			BIT(7)
    219 #define INT_BIT_ALL_OTHER_		(INT_BIT_SW_GP_ | INT_BIT_1588_)
    220 #define INT_BIT_MAS_			BIT(0)
    221 
    222 #define INT_SET				(0x784)
    223 
    224 #define INT_EN_SET			(0x788)
    225 
    226 #define INT_EN_CLR			(0x78C)
    227 
    228 #define INT_STS_R2C			(0x790)
    229 
    230 #define INT_VEC_EN_SET			(0x794)
    231 #define INT_VEC_EN_CLR			(0x798)
    232 #define INT_VEC_EN_AUTO_CLR		(0x79C)
    233 #define INT_VEC_EN_(vector_index)	BIT(0 + vector_index)
    234 
    235 #define INT_VEC_MAP0			(0x7A0)
    236 #define INT_VEC_MAP0_RX_VEC_(channel, vector)	\
    237 	(((u32)(vector)) << ((channel) << 2))
    238 
    239 #define INT_VEC_MAP1			(0x7A4)
    240 #define INT_VEC_MAP1_TX_VEC_(channel, vector)	\
    241 	(((u32)(vector)) << ((channel) << 2))
    242 
    243 #define INT_VEC_MAP2			(0x7A8)
    244 
    245 #define INT_MOD_MAP0			(0x7B0)
    246 
    247 #define INT_MOD_MAP1			(0x7B4)
    248 
    249 #define INT_MOD_MAP2			(0x7B8)
    250 
    251 #define INT_MOD_CFG0			(0x7C0)
    252 #define INT_MOD_CFG1			(0x7C4)
    253 #define INT_MOD_CFG2			(0x7C8)
    254 #define INT_MOD_CFG3			(0x7CC)
    255 #define INT_MOD_CFG4			(0x7D0)
    256 #define INT_MOD_CFG5			(0x7D4)
    257 #define INT_MOD_CFG6			(0x7D8)
    258 #define INT_MOD_CFG7			(0x7DC)
    259 
    260 #define PTP_CMD_CTL					(0x0A00)
    261 #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_			BIT(6)
    262 #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_			BIT(5)
    263 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_			BIT(4)
    264 #define PTP_CMD_CTL_PTP_CLOCK_READ_			BIT(3)
    265 #define PTP_CMD_CTL_PTP_ENABLE_				BIT(2)
    266 #define PTP_CMD_CTL_PTP_DISABLE_			BIT(1)
    267 #define PTP_CMD_CTL_PTP_RESET_				BIT(0)
    268 #define PTP_GENERAL_CONFIG				(0x0A04)
    269 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
    270 	(0x7 << (1 + ((channel) << 2)))
    271 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_	(0)
    272 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_	(1)
    273 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_	(2)
    274 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_	(3)
    275 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_	(4)
    276 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_	(5)
    277 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
    278 	(((value) & 0x7) << (1 + ((channel) << 2)))
    279 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel)	(BIT((channel) << 2))
    280 
    281 #define PTP_INT_STS				(0x0A08)
    282 #define PTP_INT_EN_SET				(0x0A0C)
    283 #define PTP_INT_EN_CLR				(0x0A10)
    284 #define PTP_INT_BIT_TX_SWTS_ERR_		BIT(13)
    285 #define PTP_INT_BIT_TX_TS_			BIT(12)
    286 #define PTP_INT_BIT_TIMER_B_			BIT(1)
    287 #define PTP_INT_BIT_TIMER_A_			BIT(0)
    288 
    289 #define PTP_CLOCK_SEC				(0x0A14)
    290 #define PTP_CLOCK_NS				(0x0A18)
    291 #define PTP_CLOCK_SUBNS				(0x0A1C)
    292 #define PTP_CLOCK_RATE_ADJ			(0x0A20)
    293 #define PTP_CLOCK_RATE_ADJ_DIR_			BIT(31)
    294 #define PTP_CLOCK_STEP_ADJ			(0x0A2C)
    295 #define PTP_CLOCK_STEP_ADJ_DIR_			BIT(31)
    296 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_		(0x3FFFFFFF)
    297 #define PTP_CLOCK_TARGET_SEC_X(channel)		(0x0A30 + ((channel) << 4))
    298 #define PTP_CLOCK_TARGET_NS_X(channel)		(0x0A34 + ((channel) << 4))
    299 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel)	(0x0A38 + ((channel) << 4))
    300 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel)	(0x0A3C + ((channel) << 4))
    301 #define PTP_LATENCY				(0x0A5C)
    302 #define PTP_LATENCY_TX_SET_(tx_latency)		(((u32)(tx_latency)) << 16)
    303 #define PTP_LATENCY_RX_SET_(rx_latency)		\
    304 	(((u32)(rx_latency)) & 0x0000FFFF)
    305 #define PTP_CAP_INFO				(0x0A60)
    306 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)	(((reg_val) & 0x00000070) >> 4)
    307 
    308 #define PTP_TX_MOD				(0x0AA4)
    309 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_	(0x10000000)
    310 
    311 #define PTP_TX_MOD2				(0x0AA8)
    312 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_	(0x00000001)
    313 
    314 #define PTP_TX_EGRESS_SEC			(0x0AAC)
    315 #define PTP_TX_EGRESS_NS			(0x0AB0)
    316 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_	(0xC0000000)
    317 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_	(0x00000000)
    318 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_	(0x40000000)
    319 #define PTP_TX_EGRESS_NS_TS_NS_MASK_		(0x3FFFFFFF)
    320 
    321 #define PTP_TX_MSG_HEADER			(0x0AB4)
    322 #define PTP_TX_MSG_HEADER_MSG_TYPE_		(0x000F0000)
    323 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_	(0x00000000)
    324 
    325 #define DMAC_CFG				(0xC00)
    326 #define DMAC_CFG_COAL_EN_			BIT(16)
    327 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_		(0x00000000)
    328 #define DMAC_CFG_MAX_READ_REQ_MASK_		(0x00000070)
    329 #define DMAC_CFG_MAX_READ_REQ_SET_(val)	\
    330 	((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
    331 #define DMAC_CFG_MAX_DSPACE_16_			(0x00000000)
    332 #define DMAC_CFG_MAX_DSPACE_32_			(0x00000001)
    333 #define DMAC_CFG_MAX_DSPACE_64_			BIT(1)
    334 #define DMAC_CFG_MAX_DSPACE_128_		(0x00000003)
    335 
    336 #define DMAC_COAL_CFG				(0xC04)
    337 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_		(0xFFF00000)
    338 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val)	\
    339 	((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
    340 #define DMAC_COAL_CFG_TIMER_TX_START_		BIT(19)
    341 #define DMAC_COAL_CFG_FLUSH_INTS_		BIT(18)
    342 #define DMAC_COAL_CFG_INT_EXIT_COAL_		BIT(17)
    343 #define DMAC_COAL_CFG_CSR_EXIT_COAL_		BIT(16)
    344 #define DMAC_COAL_CFG_TX_THRES_MASK_		(0x0000FF00)
    345 #define DMAC_COAL_CFG_TX_THRES_SET_(val)	\
    346 	((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
    347 #define DMAC_COAL_CFG_RX_THRES_MASK_		(0x000000FF)
    348 #define DMAC_COAL_CFG_RX_THRES_SET_(val)	\
    349 	(((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
    350 
    351 #define DMAC_OBFF_CFG				(0xC08)
    352 #define DMAC_OBFF_TX_THRES_MASK_		(0x0000FF00)
    353 #define DMAC_OBFF_TX_THRES_SET_(val)	\
    354 	((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
    355 #define DMAC_OBFF_RX_THRES_MASK_		(0x000000FF)
    356 #define DMAC_OBFF_RX_THRES_SET_(val)	\
    357 	(((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
    358 
    359 #define DMAC_CMD				(0xC0C)
    360 #define DMAC_CMD_SWR_				BIT(31)
    361 #define DMAC_CMD_TX_SWR_(channel)		BIT(24 + (channel))
    362 #define DMAC_CMD_START_T_(channel)		BIT(20 + (channel))
    363 #define DMAC_CMD_STOP_T_(channel)		BIT(16 + (channel))
    364 #define DMAC_CMD_RX_SWR_(channel)		BIT(8 + (channel))
    365 #define DMAC_CMD_START_R_(channel)		BIT(4 + (channel))
    366 #define DMAC_CMD_STOP_R_(channel)		BIT(0 + (channel))
    367 
    368 #define DMAC_INT_STS				(0xC10)
    369 #define DMAC_INT_EN_SET				(0xC14)
    370 #define DMAC_INT_EN_CLR				(0xC18)
    371 #define DMAC_INT_BIT_RXFRM_(channel)		BIT(16 + (channel))
    372 #define DMAC_INT_BIT_TX_IOC_(channel)		BIT(0 + (channel))
    373 
    374 #define RX_CFG_A(channel)			(0xC40 + ((channel) << 6))
    375 #define RX_CFG_A_RX_WB_ON_INT_TMR_		BIT(30)
    376 #define RX_CFG_A_RX_WB_THRES_MASK_		(0x1F000000)
    377 #define RX_CFG_A_RX_WB_THRES_SET_(val)	\
    378 	((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
    379 #define RX_CFG_A_RX_PF_THRES_MASK_		(0x001F0000)
    380 #define RX_CFG_A_RX_PF_THRES_SET_(val)	\
    381 	((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
    382 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_		(0x00001F00)
    383 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val)	\
    384 	((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
    385 #define RX_CFG_A_RX_HP_WB_EN_			BIT(5)
    386 
    387 #define RX_CFG_B(channel)			(0xC44 + ((channel) << 6))
    388 #define RX_CFG_B_TS_ALL_RX_			BIT(29)
    389 #define RX_CFG_B_RX_PAD_MASK_			(0x03000000)
    390 #define RX_CFG_B_RX_PAD_0_			(0x00000000)
    391 #define RX_CFG_B_RX_PAD_2_			(0x02000000)
    392 #define RX_CFG_B_RDMABL_512_			(0x00040000)
    393 #define RX_CFG_B_RX_RING_LEN_MASK_		(0x0000FFFF)
    394 
    395 #define RX_BASE_ADDRH(channel)			(0xC48 + ((channel) << 6))
    396 
    397 #define RX_BASE_ADDRL(channel)			(0xC4C + ((channel) << 6))
    398 
    399 #define RX_HEAD_WRITEBACK_ADDRH(channel)	(0xC50 + ((channel) << 6))
    400 
    401 #define RX_HEAD_WRITEBACK_ADDRL(channel)	(0xC54 + ((channel) << 6))
    402 
    403 #define RX_HEAD(channel)			(0xC58 + ((channel) << 6))
    404 
    405 #define RX_TAIL(channel)			(0xC5C + ((channel) << 6))
    406 #define RX_TAIL_SET_TOP_INT_EN_			BIT(30)
    407 #define RX_TAIL_SET_TOP_INT_VEC_EN_		BIT(29)
    408 
    409 #define RX_CFG_C(channel)			(0xC64 + ((channel) << 6))
    410 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_	BIT(6)
    411 #define RX_CFG_C_RX_INT_EN_R2C_			BIT(4)
    412 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_	BIT(3)
    413 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_	(0x00000007)
    414 
    415 #define TX_CFG_A(channel)			(0xD40 + ((channel) << 6))
    416 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_		BIT(30)
    417 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_		(0x10000000)
    418 #define TX_CFG_A_TX_PF_THRES_MASK_		(0x001F0000)
    419 #define TX_CFG_A_TX_PF_THRES_SET_(value)	\
    420 	((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
    421 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_		(0x00001F00)
    422 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value)	\
    423 	((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
    424 #define TX_CFG_A_TX_HP_WB_EN_			BIT(5)
    425 #define TX_CFG_A_TX_HP_WB_THRES_MASK_		(0x0000000F)
    426 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value)	\
    427 	(((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
    428 
    429 #define TX_CFG_B(channel)			(0xD44 + ((channel) << 6))
    430 #define TX_CFG_B_TDMABL_512_			(0x00040000)
    431 #define TX_CFG_B_TX_RING_LEN_MASK_		(0x0000FFFF)
    432 
    433 #define TX_BASE_ADDRH(channel)			(0xD48 + ((channel) << 6))
    434 
    435 #define TX_BASE_ADDRL(channel)			(0xD4C + ((channel) << 6))
    436 
    437 #define TX_HEAD_WRITEBACK_ADDRH(channel)	(0xD50 + ((channel) << 6))
    438 
    439 #define TX_HEAD_WRITEBACK_ADDRL(channel)	(0xD54 + ((channel) << 6))
    440 
    441 #define TX_HEAD(channel)			(0xD58 + ((channel) << 6))
    442 
    443 #define TX_TAIL(channel)			(0xD5C + ((channel) << 6))
    444 #define TX_TAIL_SET_DMAC_INT_EN_		BIT(31)
    445 #define TX_TAIL_SET_TOP_INT_EN_			BIT(30)
    446 #define TX_TAIL_SET_TOP_INT_VEC_EN_		BIT(29)
    447 
    448 #define TX_CFG_C(channel)			(0xD64 + ((channel) << 6))
    449 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_	BIT(6)
    450 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_	BIT(5)
    451 #define TX_CFG_C_TX_INT_EN_R2C_			BIT(4)
    452 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_	BIT(3)
    453 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_	(0x00000007)
    454 
    455 #define OTP_PWR_DN				(0x1000)
    456 #define OTP_PWR_DN_PWRDN_N_			BIT(0)
    457 
    458 #define OTP_ADDR_HIGH				(0x1004)
    459 #define OTP_ADDR_LOW				(0x1008)
    460 
    461 #define OTP_PRGM_DATA				(0x1010)
    462 
    463 #define OTP_PRGM_MODE				(0x1014)
    464 #define OTP_PRGM_MODE_BYTE_			BIT(0)
    465 
    466 #define OTP_READ_DATA				(0x1018)
    467 
    468 #define OTP_FUNC_CMD				(0x1020)
    469 #define OTP_FUNC_CMD_READ_			BIT(0)
    470 
    471 #define OTP_TST_CMD				(0x1024)
    472 #define OTP_TST_CMD_PRGVRFY_			BIT(3)
    473 
    474 #define OTP_CMD_GO				(0x1028)
    475 #define OTP_CMD_GO_GO_				BIT(0)
    476 
    477 #define OTP_STATUS				(0x1030)
    478 #define OTP_STATUS_BUSY_			BIT(0)
    479 
    480 /* MAC statistics registers */
    481 #define STAT_RX_FCS_ERRORS			(0x1200)
    482 #define STAT_RX_ALIGNMENT_ERRORS		(0x1204)
    483 #define STAT_RX_FRAGMENT_ERRORS			(0x1208)
    484 #define STAT_RX_JABBER_ERRORS			(0x120C)
    485 #define STAT_RX_UNDERSIZE_FRAME_ERRORS		(0x1210)
    486 #define STAT_RX_OVERSIZE_FRAME_ERRORS		(0x1214)
    487 #define STAT_RX_DROPPED_FRAMES			(0x1218)
    488 #define STAT_RX_UNICAST_BYTE_COUNT		(0x121C)
    489 #define STAT_RX_BROADCAST_BYTE_COUNT		(0x1220)
    490 #define STAT_RX_MULTICAST_BYTE_COUNT		(0x1224)
    491 #define STAT_RX_UNICAST_FRAMES			(0x1228)
    492 #define STAT_RX_BROADCAST_FRAMES		(0x122C)
    493 #define STAT_RX_MULTICAST_FRAMES		(0x1230)
    494 #define STAT_RX_PAUSE_FRAMES			(0x1234)
    495 #define STAT_RX_64_BYTE_FRAMES			(0x1238)
    496 #define STAT_RX_65_127_BYTE_FRAMES		(0x123C)
    497 #define STAT_RX_128_255_BYTE_FRAMES		(0x1240)
    498 #define STAT_RX_256_511_BYTES_FRAMES		(0x1244)
    499 #define STAT_RX_512_1023_BYTE_FRAMES		(0x1248)
    500 #define STAT_RX_1024_1518_BYTE_FRAMES		(0x124C)
    501 #define STAT_RX_GREATER_1518_BYTE_FRAMES	(0x1250)
    502 #define STAT_RX_TOTAL_FRAMES			(0x1254)
    503 #define STAT_EEE_RX_LPI_TRANSITIONS		(0x1258)
    504 #define STAT_EEE_RX_LPI_TIME			(0x125C)
    505 #define STAT_RX_COUNTER_ROLLOVER_STATUS		(0x127C)
    506 
    507 #define STAT_TX_FCS_ERRORS			(0x1280)
    508 #define STAT_TX_EXCESS_DEFERRAL_ERRORS		(0x1284)
    509 #define STAT_TX_CARRIER_ERRORS			(0x1288)
    510 #define STAT_TX_BAD_BYTE_COUNT			(0x128C)
    511 #define STAT_TX_SINGLE_COLLISIONS		(0x1290)
    512 #define STAT_TX_MULTIPLE_COLLISIONS		(0x1294)
    513 #define STAT_TX_EXCESSIVE_COLLISION		(0x1298)
    514 #define STAT_TX_LATE_COLLISIONS			(0x129C)
    515 #define STAT_TX_UNICAST_BYTE_COUNT		(0x12A0)
    516 #define STAT_TX_BROADCAST_BYTE_COUNT		(0x12A4)
    517 #define STAT_TX_MULTICAST_BYTE_COUNT		(0x12A8)
    518 #define STAT_TX_UNICAST_FRAMES			(0x12AC)
    519 #define STAT_TX_BROADCAST_FRAMES		(0x12B0)
    520 #define STAT_TX_MULTICAST_FRAMES		(0x12B4)
    521 #define STAT_TX_PAUSE_FRAMES			(0x12B8)
    522 #define STAT_TX_64_BYTE_FRAMES			(0x12BC)
    523 #define STAT_TX_65_127_BYTE_FRAMES		(0x12C0)
    524 #define STAT_TX_128_255_BYTE_FRAMES		(0x12C4)
    525 #define STAT_TX_256_511_BYTES_FRAMES		(0x12C8)
    526 #define STAT_TX_512_1023_BYTE_FRAMES		(0x12CC)
    527 #define STAT_TX_1024_1518_BYTE_FRAMES		(0x12D0)
    528 #define STAT_TX_GREATER_1518_BYTE_FRAMES	(0x12D4)
    529 #define STAT_TX_TOTAL_FRAMES			(0x12D8)
    530 #define STAT_EEE_TX_LPI_TRANSITIONS		(0x12DC)
    531 #define STAT_EEE_TX_LPI_TIME			(0x12E0)
    532 #define STAT_TX_COUNTER_ROLLOVER_STATUS		(0x12FC)
    533 
    534 /* End of Register definitions */
    535 
    536 #define LAN743X_MAX_RX_CHANNELS		(4)
    537 #define LAN743X_MAX_TX_CHANNELS		(1)
    538 struct lan743x_adapter;
    539 
    540 #define LAN743X_USED_RX_CHANNELS	(4)
    541 #define LAN743X_USED_TX_CHANNELS	(1)
    542 #define LAN743X_INT_MOD	(400)
    543 
    544 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
    545 #error Invalid LAN743X_USED_RX_CHANNELS
    546 #endif
    547 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
    548 #error Invalid LAN743X_USED_TX_CHANNELS
    549 #endif
    550 
    551 /* PCI */
    552 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
    553 #define PCI_VENDOR_ID_SMSC		PCI_VENDOR_ID_EFAR
    554 #define PCI_DEVICE_ID_SMSC_LAN7430	(0x7430)
    555 #define PCI_DEVICE_ID_SMSC_LAN7431	(0x7431)
    556 
    557 #define PCI_CONFIG_LENGTH		(0x1000)
    558 
    559 /* CSR */
    560 #define CSR_LENGTH					(0x2000)
    561 
    562 #define LAN743X_CSR_FLAG_IS_A0				BIT(0)
    563 #define LAN743X_CSR_FLAG_IS_B0				BIT(1)
    564 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR	BIT(8)
    565 
    566 struct lan743x_csr {
    567 	u32 flags;
    568 	u8 __iomem *csr_address;
    569 	u32 id_rev;
    570 	u32 fpga_rev;
    571 };
    572 
    573 /* INTERRUPTS */
    574 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
    575 
    576 #define LAN743X_VECTOR_FLAG_IRQ_SHARED			BIT(0)
    577 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ		BIT(1)
    578 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C		BIT(2)
    579 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C		BIT(3)
    580 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK		BIT(4)
    581 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR		BIT(5)
    582 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C		BIT(6)
    583 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR		BIT(7)
    584 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET		BIT(8)
    585 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR	BIT(9)
    586 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET	BIT(10)
    587 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR	BIT(11)
    588 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET	BIT(12)
    589 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR	BIT(13)
    590 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET	BIT(14)
    591 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR	BIT(15)
    592 
    593 struct lan743x_vector {
    594 	int			irq;
    595 	u32			flags;
    596 	struct lan743x_adapter	*adapter;
    597 	int			vector_index;
    598 	u32			int_mask;
    599 	lan743x_vector_handler	handler;
    600 	void			*context;
    601 };
    602 
    603 #define LAN743X_MAX_VECTOR_COUNT	(8)
    604 
    605 struct lan743x_intr {
    606 	int			flags;
    607 
    608 	unsigned int		irq;
    609 
    610 	struct lan743x_vector	vector_list[LAN743X_MAX_VECTOR_COUNT];
    611 	int			number_of_vectors;
    612 	bool			using_vectors;
    613 
    614 	int			software_isr_flag;
    615 };
    616 
    617 #define LAN743X_MAX_FRAME_SIZE			(9 * 1024)
    618 
    619 /* PHY */
    620 struct lan743x_phy {
    621 	bool	fc_autoneg;
    622 	u8	fc_request_control;
    623 };
    624 
    625 /* TX */
    626 struct lan743x_tx_descriptor;
    627 struct lan743x_tx_buffer_info;
    628 
    629 #define GPIO_QUEUE_STARTED		(0)
    630 #define GPIO_TX_FUNCTION		(1)
    631 #define GPIO_TX_COMPLETION		(2)
    632 #define GPIO_TX_FRAGMENT		(3)
    633 
    634 #define TX_FRAME_FLAG_IN_PROGRESS	BIT(0)
    635 
    636 #define TX_TS_FLAG_TIMESTAMPING_ENABLED	BIT(0)
    637 #define TX_TS_FLAG_ONE_STEP_SYNC	BIT(1)
    638 
    639 struct lan743x_tx {
    640 	struct lan743x_adapter *adapter;
    641 	u32	ts_flags;
    642 	u32	vector_flags;
    643 	int	channel_number;
    644 
    645 	int	ring_size;
    646 	size_t	ring_allocation_size;
    647 	struct lan743x_tx_descriptor *ring_cpu_ptr;
    648 	dma_addr_t ring_dma_ptr;
    649 	/* ring_lock: used to prevent concurrent access to tx ring */
    650 	spinlock_t ring_lock;
    651 	u32		frame_flags;
    652 	u32		frame_first;
    653 	u32		frame_data0;
    654 	u32		frame_tail;
    655 
    656 	struct lan743x_tx_buffer_info *buffer_info;
    657 
    658 	u32		*head_cpu_ptr;
    659 	dma_addr_t	head_dma_ptr;
    660 	int		last_head;
    661 	int		last_tail;
    662 
    663 	struct napi_struct napi;
    664 
    665 	struct sk_buff *overflow_skb;
    666 };
    667 
    668 void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
    669 				      bool enable_timestamping,
    670 				      bool enable_onestep_sync);
    671 
    672 /* RX */
    673 struct lan743x_rx_descriptor;
    674 struct lan743x_rx_buffer_info;
    675 
    676 struct lan743x_rx {
    677 	struct lan743x_adapter *adapter;
    678 	u32	vector_flags;
    679 	int	channel_number;
    680 
    681 	int	ring_size;
    682 	size_t	ring_allocation_size;
    683 	struct lan743x_rx_descriptor *ring_cpu_ptr;
    684 	dma_addr_t ring_dma_ptr;
    685 
    686 	struct lan743x_rx_buffer_info *buffer_info;
    687 
    688 	u32		*head_cpu_ptr;
    689 	dma_addr_t	head_dma_ptr;
    690 	u32		last_head;
    691 	u32		last_tail;
    692 
    693 	struct napi_struct napi;
    694 
    695 	u32		frame_count;
    696 };
    697 
    698 struct lan743x_adapter {
    699 	struct net_device       *netdev;
    700 	struct mii_bus		*mdiobus;
    701 	int                     msg_enable;
    702 #ifdef CONFIG_PM
    703 	u32			wolopts;
    704 #endif
    705 	struct pci_dev		*pdev;
    706 	struct lan743x_csr      csr;
    707 	struct lan743x_intr     intr;
    708 
    709 	/* lock, used to prevent concurrent access to data port */
    710 	struct mutex		dp_lock;
    711 
    712 	struct lan743x_gpio	gpio;
    713 	struct lan743x_ptp	ptp;
    714 
    715 	u8			mac_address[ETH_ALEN];
    716 
    717 	struct lan743x_phy      phy;
    718 	struct lan743x_tx       tx[LAN743X_MAX_TX_CHANNELS];
    719 	struct lan743x_rx       rx[LAN743X_MAX_RX_CHANNELS];
    720 
    721 #define LAN743X_ADAPTER_FLAG_OTP		BIT(0)
    722 	u32			flags;
    723 };
    724 
    725 #define LAN743X_COMPONENT_FLAG_RX(channel)  BIT(20 + (channel))
    726 
    727 #define INTR_FLAG_IRQ_REQUESTED(vector_index)	BIT(0 + vector_index)
    728 #define INTR_FLAG_MSI_ENABLED			BIT(8)
    729 #define INTR_FLAG_MSIX_ENABLED			BIT(9)
    730 
    731 #define MAC_MII_READ            1
    732 #define MAC_MII_WRITE           0
    733 
    734 #define PHY_FLAG_OPENED     BIT(0)
    735 #define PHY_FLAG_ATTACHED   BIT(1)
    736 
    737 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
    738 #define DMA_ADDR_HIGH32(dma_addr)   ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
    739 #else
    740 #define DMA_ADDR_HIGH32(dma_addr)   ((u32)(0))
    741 #endif
    742 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
    743 #define DMA_DESCRIPTOR_SPACING_16       (16)
    744 #define DMA_DESCRIPTOR_SPACING_32       (32)
    745 #define DMA_DESCRIPTOR_SPACING_64       (64)
    746 #define DMA_DESCRIPTOR_SPACING_128      (128)
    747 #define DEFAULT_DMA_DESCRIPTOR_SPACING  (L1_CACHE_BYTES)
    748 
    749 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
    750 	(((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
    751 #define DMAC_CHANNEL_STATE_INITIAL      DMAC_CHANNEL_STATE_SET(0, 0)
    752 #define DMAC_CHANNEL_STATE_STARTED      DMAC_CHANNEL_STATE_SET(1, 0)
    753 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
    754 #define DMAC_CHANNEL_STATE_STOPPED      DMAC_CHANNEL_STATE_SET(0, 1)
    755 
    756 /* TX Descriptor bits */
    757 #define TX_DESC_DATA0_DTYPE_MASK_		(0xC0000000)
    758 #define TX_DESC_DATA0_DTYPE_DATA_		(0x00000000)
    759 #define TX_DESC_DATA0_DTYPE_EXT_		(0x40000000)
    760 #define TX_DESC_DATA0_FS_			(0x20000000)
    761 #define TX_DESC_DATA0_LS_			(0x10000000)
    762 #define TX_DESC_DATA0_EXT_			(0x08000000)
    763 #define TX_DESC_DATA0_IOC_			(0x04000000)
    764 #define TX_DESC_DATA0_ICE_			(0x00400000)
    765 #define TX_DESC_DATA0_IPE_			(0x00200000)
    766 #define TX_DESC_DATA0_TPE_			(0x00100000)
    767 #define TX_DESC_DATA0_FCS_			(0x00020000)
    768 #define TX_DESC_DATA0_TSE_			(0x00010000)
    769 #define TX_DESC_DATA0_BUF_LENGTH_MASK_		(0x0000FFFF)
    770 #define TX_DESC_DATA0_EXT_LSO_			(0x00200000)
    771 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_	(0x000FFFFF)
    772 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_	(0x3FFF0000)
    773 
    774 struct lan743x_tx_descriptor {
    775 	u32     data0;
    776 	u32     data1;
    777 	u32     data2;
    778 	u32     data3;
    779 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
    780 
    781 #define TX_BUFFER_INFO_FLAG_ACTIVE		BIT(0)
    782 #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED	BIT(1)
    783 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC		BIT(2)
    784 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT	BIT(3)
    785 struct lan743x_tx_buffer_info {
    786 	int flags;
    787 	struct sk_buff *skb;
    788 	dma_addr_t      dma_ptr;
    789 	unsigned int    buffer_length;
    790 };
    791 
    792 #define LAN743X_TX_RING_SIZE    (50)
    793 
    794 /* OWN bit is set. ie, Descs are owned by RX DMAC */
    795 #define RX_DESC_DATA0_OWN_                (0x00008000)
    796 /* OWN bit is clear. ie, Descs are owned by host */
    797 #define RX_DESC_DATA0_FS_                 (0x80000000)
    798 #define RX_DESC_DATA0_LS_                 (0x40000000)
    799 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_  (0x3FFF0000)
    800 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0)	\
    801 	(((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
    802 #define RX_DESC_DATA0_EXT_                (0x00004000)
    803 #define RX_DESC_DATA0_BUF_LENGTH_MASK_    (0x00003FFF)
    804 #define RX_DESC_DATA2_TS_NS_MASK_         (0x3FFFFFFF)
    805 
    806 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
    807 #error NET_IP_ALIGN must be 0 or 2
    808 #endif
    809 
    810 #define RX_HEAD_PADDING		NET_IP_ALIGN
    811 
    812 struct lan743x_rx_descriptor {
    813 	u32     data0;
    814 	u32     data1;
    815 	u32     data2;
    816 	u32     data3;
    817 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
    818 
    819 #define RX_BUFFER_INFO_FLAG_ACTIVE      BIT(0)
    820 struct lan743x_rx_buffer_info {
    821 	int flags;
    822 	struct sk_buff *skb;
    823 
    824 	dma_addr_t      dma_ptr;
    825 	unsigned int    buffer_length;
    826 };
    827 
    828 #define LAN743X_RX_RING_SIZE        (65)
    829 
    830 #define RX_PROCESS_RESULT_NOTHING_TO_DO     (0)
    831 #define RX_PROCESS_RESULT_PACKET_RECEIVED   (1)
    832 #define RX_PROCESS_RESULT_PACKET_DROPPED    (2)
    833 
    834 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);
    835 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);
    836 
    837 #endif /* _LAN743X_H */